BMC/Intel-BMC/linux.git/drivers/mailbox, branch dev-5.15-intel

mailbox: imx: fix wakeup failure from freeze mode

2022-04-08T12:24:10+00:00

commit 892cb524ae8a27bf5e42f711318371acd9a9f74a upstream. Since IRQF_NO_SUSPEND used for imx mailbox driver, that means this irq can't be used for wakeup source so that can't wakeup from freeze mode. Add pm_system_wakeup() to wakeup from freeze mode. Fixes: b7b2796b9b31e("mailbox: imx: ONLY IPC MU needs IRQF_NO_SUSPEND flag") Reviewed-by: Jacky Bai Reviewed-by: Peng Fan Signed-off-by: Robin Gong Signed-off-by: Peng Fan Signed-off-by: Jassi Brar Signed-off-by: Greg Kroah-Hartman

mailbox: imx: fix crash in resume on i.mx8ulp

2022-04-08T12:23:48+00:00

[ Upstream commit 8219efd08a0aa1d7944bdb66d84ba57549258968 ] check 'priv->clk' before 'imx_mu_read()' otherwise crash happens on i.mx8ulp, since clock not enabled. Fixes: 4f0b776ef5831 ("mailbox: imx-mailbox: support i.MX8ULP MU") Reviewed-by: Jacky Bai Signed-off-by: Robin Gong Signed-off-by: Peng Fan Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: tegra-hsp: Flush whole channel

2022-04-08T12:22:59+00:00

commit 60de2d2dc284e0dd1c2c897d08625bde24ef3454 upstream. The txdone can re-fill the mailbox. Keep polling the mailbox during the flush until all the messages have been delivered. This fixes an issue with the Tegra Combined UART (TCU) where output can get truncated under high traffic load. Signed-off-by: Pekka Pessi Tested-by: Jon Hunter Fixes: 91b1b1c3da8a ("mailbox: tegra-hsp: Add support for shared mailboxes") Cc: stable@vger.kernel.org Signed-off-by: Thierry Reding Reviewed-by: Jon Hunter Signed-off-by: Jassi Brar Signed-off-by: Greg Kroah-Hartman

mailbox: change mailbox-mpfs compatible string

2022-01-27T10:05:05+00:00

[ Upstream commit f10b1fc0161cd99e54c5687fcc63368aa255e05e ] The Polarfire SoC is currently using two different compatible string prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in its system controller in order to match the compatible string used in the soc binding and device tree. Signed-off-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: fix gce_num of mt8192 driver data

2022-01-27T10:04:21+00:00

[ Upstream commit 35ca43710f792ce183312fdc7e4b2bb0b721a173 ] Because mt8192 only have 1 gce, the gce_num should be 1. Fixes: 85dfdbfc13ea ("mailbox: cmdq: add multi-gce clocks support for mt8195") Signed-off-by: jason-jh.lin Reviewed-by: Matthias Brugger Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: mtk-cmdq: Fix local clock ID usage

2021-11-18T18:16:35+00:00

[ Upstream commit 0a5ad4322927ee4aaba6facc0e4faf1ab6c0d48e ] In the probe function, the clock IDs were pointed to local variables which should only be used in the same code block, and any access to them after the probing stage becomes an use-after-free case. Since there are only limited variants of the gce clock names so far, we can just declare them as static constants to fix the issue. Fixes: 85dfdbfc13ea ("mailbox: cmdq: add multi-gce clocks support for mt8195") Signed-off-by: Fei Shao Reviewed-by: Tzung-Bi Shih Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: mtk-cmdq: Validate alias_id on probe

2021-11-18T18:16:34+00:00

[ Upstream commit 5c154b6a51c2d2d7f266b3ef49b7dd1dc8cb5b65 ] of_alias_get_id() may return -ENODEV which leads to illegal access to the cmdq->clocks array. Adding a check over alias_id to prevent the unexpected behavior. Fixes: 85dfdbfc13ea ("mailbox: cmdq: add multi-gce clocks support for mt8195") Signed-off-by: Fei Shao Reviewed-by: Tzung-Bi Shih Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: Remove WARN_ON for async_cb.cb in cmdq_exec_done

2021-11-18T18:16:34+00:00

[ Upstream commit ce1537fe288469bf68ee0aabdb860a790b4755ef ] Because mtk_drm_crtc_update_config is not using cmdq_pkt_flush_async, it won't have pkt->async_cb.cb anymore. So remove the WARN_ON check of pkt->async_cb.cb at cmdq_exec_done. Fixes: 1b6b0ce2240e ("mailbox: mtk-cmdq: Use mailbox rx_callback") Signed-off-by: jason-jh.lin Reviewed-by: Chun-Kuang Hu Tested-by: Enric Balletbo i Serra Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: cmdq: add multi-gce clocks support for mt8195

2021-09-01T03:57:45+00:00

For the design of GCE hardware event signal transportation, evnet rx will send the event signal to all GCE event merges after receiving the event signal from the other hardware. Because GCE event merges need to response to event rx, their clocks must be enabled at that time. To make sure all the gce clock is enabled while receiving the hardware event, each cmdq mailbox should enable or disable the others gce clk at the same time. Signed-off-by: jason-jh.lin Signed-off-by: Jassi Brar

mailbox: cmdq: add mediatek mailbox support for mt8195

2021-09-01T03:57:39+00:00

Add mt8195 compatible name in the driver data of cmdq mailbox driver. Signed-off-by: jason-jh.lin Signed-off-by: Jassi Brar