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<title>BMC/Intel-BMC/linux.git/drivers/iommu, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
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<updated>2015-07-31T13:15:41+00:00</updated>
<entry>
<title>iommu/amd: Allow non-ATS devices in IOMMUv2 domains</title>
<updated>2015-07-31T13:15:41+00:00</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2015-07-30T09:24:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=1c1cc454aa694a89572689515fdaaf27b8c9f42a'/>
<id>urn:sha1:1c1cc454aa694a89572689515fdaaf27b8c9f42a</id>
<content type='text'>
With the grouping of multi-function devices a non-ATS
capable device might also end up in the same domain as an
IOMMUv2 capable device.
So handle this situation gracefully and don't consider it a
bug anymore.

Tested-by: Oded Gabbay &lt;oded.gabbay@gmail.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu/amd: Set global dma_ops if swiotlb is disabled</title>
<updated>2015-07-30T08:28:48+00:00</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2015-07-28T14:58:51+00:00</published>
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<id>urn:sha1:52717828356b643a1650fca845b4af488a954cca</id>
<content type='text'>
Some AMD systems also have non-PCI devices which can do DMA.
Those can't be handled by the AMD IOMMU, as the hardware can
only handle PCI. These devices would end up with no dma_ops,
as neither the per-device nor the global dma_ops will get
set. SWIOTLB provides global dma_ops when it is active, so
make sure there are global dma_ops too when swiotlb is
disabled.

Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu/amd: Use swiotlb in passthrough mode</title>
<updated>2015-07-30T08:28:48+00:00</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2015-07-28T14:58:50+00:00</published>
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<id>urn:sha1:323023245771589c53869396e3297c703d347852</id>
<content type='text'>
In passthrough mode (iommu=pt) all devices are identity
mapped. If a device does not support 64bit DMA it might
still need remapping. Make sure swiotlb is initialized to
provide this remapping.

Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu/amd: Allow non-IOMMUv2 devices in IOMMUv2 domains</title>
<updated>2015-07-30T08:28:48+00:00</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2015-07-28T14:58:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=02ca20212f0dde5c90be8de19cc159726b5561aa'/>
<id>urn:sha1:02ca20212f0dde5c90be8de19cc159726b5561aa</id>
<content type='text'>
Since devices with IOMMUv2 functionality might be in the
same group as devices without it, allow those devices in
IOMMUv2 domains too.
Otherwise attaching the group with the IOMMUv2 device to the
domain will fail.

Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu/amd: Use iommu core for passthrough mode</title>
<updated>2015-07-30T08:28:48+00:00</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2015-07-28T14:58:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=1e6a7b04c033fe76ec7fe746ef6a3b22ab9502b2'/>
<id>urn:sha1:1e6a7b04c033fe76ec7fe746ef6a3b22ab9502b2</id>
<content type='text'>
Remove the AMD IOMMU driver implementation for passthrough
mode and rely on the new iommu core features for that.

Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu/amd: Use iommu_attach_group()</title>
<updated>2015-07-30T08:28:48+00:00</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2015-07-28T14:58:47+00:00</published>
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<id>urn:sha1:55c99a4dc50fb749076592e8c66c235ca0124360</id>
<content type='text'>
Since the conversion to default domains the
iommu_attach_device function only works for devices with
their own group. But this isn't always true for current
IOMMUv2 capable devices, so use iommu_attach_group instead.

Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu/vt-d: Fix VM domain ID leak</title>
<updated>2015-07-23T12:17:39+00:00</updated>
<author>
<name>Alex Williamson</name>
<email>alex.williamson@redhat.com</email>
</author>
<published>2015-07-14T20:48:53+00:00</published>
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<id>urn:sha1:46ebb7af7b93792de65e124e1ab8b89a108a41f2</id>
<content type='text'>
This continues the attempt to fix commit fb170fb4c548 ("iommu/vt-d:
Introduce helper functions to make code symmetric for readability").
The previous attempt in commit 71684406905f ("iommu/vt-d: Detach
domain *only* from attached iommus") overlooked the fact that
dmar_domain.iommu_bmp gets cleared for VM domains when devices are
detached:

intel_iommu_detach_device
  domain_remove_one_dev_info
    domain_detach_iommu

The domain is detached from the iommu, but the iommu is still attached
to the domain, for whatever reason.  Thus when we get to domain_exit(),
we can't rely on iommu_bmp for VM domains to find the active iommus,
we must check them all.  Without that, the corresponding bit in
intel_iommu.domain_ids doesn't get cleared and repeated VM domain
creation and destruction will run out of domain IDs.  Meanwhile we
still can't call iommu_detach_domain() on arbitrary non-VM domains or
we risk clearing in-use domain IDs, as 71684406905f attempted to
address.

It's tempting to modify iommu_detach_domain() to test the domain
iommu_bmp, but the call ordering from domain_remove_one_dev_info()
prevents it being able to work as fb170fb4c548 seems to have intended.
Caching of unused VM domains on the iommu object seems to be the root
of the problem, but this code is far too fragile for that kind of
rework to be proposed for stable, so we simply revert this chunk to
its state prior to fb170fb4c548.

Fixes: fb170fb4c548 ("iommu/vt-d: Introduce helper functions to make
                      code symmetric for readability")
Fixes: 71684406905f ("iommu/vt-d: Detach domain *only* from attached
                      iommus")
Signed-off-by: Alex Williamson &lt;alex.williamson@redhat.com&gt;
Cc: Jiang Liu &lt;jiang.liu@linux.intel.com&gt;
Cc: stable@vger.kernel.org # v3.17+
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu/arm-smmu: Skip the execution of CMD_PREFETCH_CONFIG</title>
<updated>2015-07-08T16:24:39+00:00</updated>
<author>
<name>Zhen Lei</name>
<email>thunder.leizhen@huawei.com</email>
</author>
<published>2015-07-07T03:30:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=5e92946c39ca6abc65e34775a93cc1d1a819c0e3'/>
<id>urn:sha1:5e92946c39ca6abc65e34775a93cc1d1a819c0e3</id>
<content type='text'>
Hisilicon SMMUv3 devices treat CMD_PREFETCH_CONFIG as a illegal command,
execute it will trigger GERROR interrupt. Although the gerror code manage
to turn the prefetch into a SYNC, and the system can continue to run
normally, but it's ugly to print error information.

Signed-off-by: Zhen Lei &lt;thunder.leizhen@huawei.com&gt;
[will: extended binding documentation]
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>iommu/arm-smmu: Enlarge STRTAB_L1_SZ_SHIFT to support larger sidsize</title>
<updated>2015-07-08T16:24:39+00:00</updated>
<author>
<name>Zhen Lei</name>
<email>thunder.leizhen@huawei.com</email>
</author>
<published>2015-07-07T03:30:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=e2f4c2330f08ba73d9a3c919a3d6ca33dce7d2c2'/>
<id>urn:sha1:e2f4c2330f08ba73d9a3c919a3d6ca33dce7d2c2</id>
<content type='text'>
Because we will choose the minimum value between STRTAB_L1_SZ_SHIFT and
IDR1.SIDSIZE, so enlarge STRTAB_L1_SZ_SHIFT will not impact the platforms
whose IDR1.SIDSIZE is smaller than old STRTAB_L1_SZ_SHIFT value.

Signed-off-by: Zhen Lei &lt;thunder.leizhen@huawei.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT</title>
<updated>2015-07-08T16:24:39+00:00</updated>
<author>
<name>Zhen Lei</name>
<email>thunder.leizhen@huawei.com</email>
</author>
<published>2015-06-26T08:32:59+00:00</published>
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<id>urn:sha1:5d58c6207c300340151931ad9c2cdea2d1685dc4</id>
<content type='text'>
The arm64 CPU architecture defines TCR[8:11] as holding the inner and
outer memory attributes for TTBR0.

This patch fixes the ARM SMMUv3 driver to pack these bits into the
context descriptor, rather than picking up the TTBR1 attributes as it
currently does.

Signed-off-by: Zhen Lei &lt;thunder.leizhen@huawei.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
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