Intel OpenBMC Linux kernel source tree (mirror) https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev 2015-01-19T14:46:45+00:00 2015-01-19T14:46:45+00:00 Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com 2014-12-14T21:34:50+00:00 urn:sha1:c896c132b01895fd1445d178e36155b671c6f9ee The quirk causes the Non-Secure bit to be set in all page table entries. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Will Deacon <will.deacon@arm.com> 2015-01-19T14:46:44+00:00 Will Deacon will.deacon@arm.com 2014-11-14T17:18:23+00:00 urn:sha1:e1d3c0fd701df831169b116cd5c5d6203ac07f70 A number of IOMMUs found in ARM SoCs can walk architecture-compatible page tables. This patch adds a generic allocator for Stage-1 and Stage-2 v7/v8 long-descriptor page tables. 4k, 16k and 64k pages are supported, with up to 4-levels of walk to cover a 48-bit address space. Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Will Deacon <will.deacon@arm.com> 2015-01-19T14:46:43+00:00 Will Deacon will.deacon@arm.com 2014-11-14T17:16:49+00:00 urn:sha1:fdb1d7be7c4d452e9735aeb2b60ae8a2fcf0a514 This patch introduces a generic framework for allocating page tables for an IOMMU. There are a number of reasons we want to do this: - It avoids duplication of complex table management code in IOMMU drivers that use the same page table format - It removes any coupling with the CPU table format (and even the architecture!) - It defines an API for IOMMU TLB maintenance Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Will Deacon <will.deacon@arm.com>