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<title>BMC/Intel-BMC/linux.git/drivers/infiniband/ulp/iser, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
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<updated>2015-06-12T18:49:10+00:00</updated>
<entry>
<title>IB/core: Change ib_create_cq to use struct ib_cq_init_attr</title>
<updated>2015-06-12T18:49:10+00:00</updated>
<author>
<name>Matan Barak</name>
<email>matanb@mellanox.com</email>
</author>
<published>2015-06-11T13:35:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=8e37210b38fb7d6aa06aebde763316ee955d44c0'/>
<id>urn:sha1:8e37210b38fb7d6aa06aebde763316ee955d44c0</id>
<content type='text'>
Currently, ib_create_cq uses cqe and comp_vecotr instead
of the extendible ib_cq_init_attr struct.

Earlier patches already changed the vendors to work with
ib_cq_init_attr. This patch changes the consumers too.

Signed-off-by: Matan Barak &lt;matanb@mellanox.com&gt;
Signed-off-by: Or Gerlitz &lt;ogerlitz@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/iser: Align to generic logging helpers</title>
<updated>2015-05-18T17:44:22+00:00</updated>
<author>
<name>Sagi Grimberg</name>
<email>sagig@mellanox.com</email>
</author>
<published>2015-05-18T10:40:30+00:00</published>
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<id>urn:sha1:871e00afa444be6908c887e61f0070c3524b3f68</id>
<content type='text'>
Signed-off-by: Sagi Grimberg &lt;sagig@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/iser: Rewrite bounce buffer code path</title>
<updated>2015-04-15T20:07:14+00:00</updated>
<author>
<name>Sagi Grimberg</name>
<email>sagig@mellanox.com</email>
</author>
<published>2015-04-14T15:08:28+00:00</published>
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<id>urn:sha1:ba943fb237ea48b01e3229f10cdb2a4274978a2d</id>
<content type='text'>
In some rare cases, IO operations may be not aligned to page
boundaries. This prevents iser from performing fast memory
registration. In order to overcome that iser uses a bounce
buffer to carry the transaction. We basically allocate a buffer
in the size of the transaction and perform a copy.

The buffer allocation using kmalloc is too restrictive since it
requires higher order (atomic) allocations for large transactions
(which may result in memory exhaustion fairly fast for some workloads).
We rewrite the bounce buffer code path to allocate scattered pages
and perform a copy between the transaction sg and the bounce sg.

Reported-by: Alex Lyakas &lt;alex@zadarastorage.com&gt;
Signed-off-by: Sagi Grimberg &lt;sagig@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/iser: Bump version to 1.6</title>
<updated>2015-04-15T20:07:13+00:00</updated>
<author>
<name>Sagi Grimberg</name>
<email>sagig@mellanox.com</email>
</author>
<published>2015-04-14T15:08:27+00:00</published>
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<id>urn:sha1:4fcd1470a05253236576a2d166ddd6d5b5c936fc</id>
<content type='text'>
Signed-off-by: Sagi Grimberg &lt;sagig@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/iser: Remove code duplication for a single DMA entry</title>
<updated>2015-04-15T20:07:13+00:00</updated>
<author>
<name>Sagi Grimberg</name>
<email>sagig@mellanox.com</email>
</author>
<published>2015-04-14T15:08:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=ad1e5672429eadd5a7f9613bf2e59546a2eeef13'/>
<id>urn:sha1:ad1e5672429eadd5a7f9613bf2e59546a2eeef13</id>
<content type='text'>
In singleton scatterlists, DMA memory registration code
is taken both for Fastreg and FMR code paths. Move it to
a function.

This patch does not change any functionality.

Signed-off-by: Sagi Grimberg &lt;sagig@mellanox.com&gt;
Signed-off-by: Adir Lev &lt;adirl@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/iser: Pass struct iser_mem_reg to iser_fast_reg_mr and iser_reg_sig_mr</title>
<updated>2015-04-15T20:07:13+00:00</updated>
<author>
<name>Sagi Grimberg</name>
<email>sagig@mellanox.com</email>
</author>
<published>2015-04-14T15:08:25+00:00</published>
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<id>urn:sha1:6ef8bb837dd7e60f078084d4842a43fd163fb4a2</id>
<content type='text'>
Instead of passing ib_sge as output variable, we pass the mem_reg
pointer to have the routines fill the rkey as well. This reduces
code duplication and extra assignments. This is a preparation step
to unify some registration logics together. Also, pass iser_fast_reg_mr
the fastreg descriptor directly.

This patch does not change any functionality.

Signed-off-by: Sagi Grimberg &lt;sagig@mellanox.com&gt;
Signed-off-by: Adir Lev &lt;adirl@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/iser: Modify struct iser_mem_reg members</title>
<updated>2015-04-15T20:07:13+00:00</updated>
<author>
<name>Sagi Grimberg</name>
<email>sagig@mellanox.com</email>
</author>
<published>2015-04-14T15:08:24+00:00</published>
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<id>urn:sha1:90a6684c30918786446fd062c7422a4098926891</id>
<content type='text'>
No need to keep lkey, va, len variables, we can keep
them as struct ib_sge. This will help when we change the
memory registration logic.

This patch does not change any functionality.

Signed-off-by: Sagi Grimberg &lt;sagig@mellanox.com&gt;
Signed-off-by: Adir Lev &lt;adirl@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/iser: Make fastreg pool cache friendly</title>
<updated>2015-04-15T20:07:13+00:00</updated>
<author>
<name>Sagi Grimberg</name>
<email>sagig@mellanox.com</email>
</author>
<published>2015-04-14T15:08:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=8b95aa2c1bf8c936e5b0e9096b180a3e4f5327ff'/>
<id>urn:sha1:8b95aa2c1bf8c936e5b0e9096b180a3e4f5327ff</id>
<content type='text'>
Memory regions are resources that are saved
in the device caches. Increase the probability for
a cache hit by adding the MRU descriptor to pool
head.

Signed-off-by: Sagi Grimberg &lt;sagig@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/iser: Move PI context alloc/free to routines</title>
<updated>2015-04-15T20:07:13+00:00</updated>
<author>
<name>Sagi Grimberg</name>
<email>sagig@mellanox.com</email>
</author>
<published>2015-04-14T15:08:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=4dec2a27e385ac753d754af69f344625f5c50576'/>
<id>urn:sha1:4dec2a27e385ac753d754af69f344625f5c50576</id>
<content type='text'>
Make iser_[create|destroy]_fastreg_desc shorter, more
readable and easily extendable.

This patch does not change any functionality.

Signed-off-by: Sagi Grimberg &lt;sagig@mellanox.com&gt;
Signed-off-by: Adir Lev &lt;adirl@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/iser: Move fastreg descriptor pool get/put to helper functions</title>
<updated>2015-04-15T20:07:13+00:00</updated>
<author>
<name>Sagi Grimberg</name>
<email>sagig@mellanox.com</email>
</author>
<published>2015-04-14T15:08:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=bd8b944eeeb06f5dac705d2357af3800395174eb'/>
<id>urn:sha1:bd8b944eeeb06f5dac705d2357af3800395174eb</id>
<content type='text'>
Instead of open-coding connection fastreg pool get/put,
we introduce iser_reg_desc[get|put] helpers.

We aren't setting these static as this will be a per-device
routine later on. Also, cleanup iser_unreg_rdma_mem_fastreg
a bit.

This patch does not change any functionality.

Signed-off-by: Sagi Grimberg &lt;sagig@mellanox.com&gt;
Signed-off-by: Adir Lev &lt;adirl@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
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