BMC/Intel-BMC/linux.git/drivers/i2c, branch dev-5.14-intel

i2c: aspeed: fix interrupt handling on some abnormal cases

2021-10-19T22:10:39+00:00

These two exceptional cases were rarely observed in a slave device reset or in a peer master reset conditions. 1. aspeed-i2c-bus 1e78a480.i2c-bus: irq handled != irq. expected 0x00000030, but was 0x00000020 when master goes from ASPEED_I2C_MASTER_STOP to ASPEED_I2C_MASTER_INACTIVE state due to an ASPEED_I2CD_INTR_ABNORMAL event. In this case, ASPEED_I2CD_INTR_NORMAL_STOP should be simply ignored without printing out the error message. 2. aspeed-i2c-bus 1e78a480.i2c-bus: irq handled != irq. expected 0x00000010, but was 0x00000000 when master already went to ASPEED_I2C_MASTER_INACTIVE. H/W sends one additional ASPEED_I2CD_INTR_NORMAL_STOP event but it's a garbage because driver is already in inactive state so filter it off from the error message printing out. Signed-off-by: Jae Hyun Yoo Change-Id: I94794a9612a7e8db445591e490bad6adae0faacf

i2c: aspeed: clear slave addresses in probe

2021-10-19T22:10:35+00:00

Initial value of I2CD18 is undefined according to the datasheet so this commit adds the I2CD18 register clearing code into bus initialization function to prevent any unexpected slave match events. Signed-off-by: Jae Hyun Yoo

i2c: aspeed: fix arbitration loss handling logic

2021-10-19T22:10:33+00:00

When an arbitration loss happens in a multi-master bus, driver drops the packet induce I2C subsystem to retry the transaction by returning -EAGAIN. During this handling, tx_ack comes along sometimes and it causes this this garbage printing out: aspeed-i2c-bus 1e78a400.i2c-bus: irq handled != irq. expected 0x00000009, but was 0x00000008 To fix this issue, this commit adds the tx_ack flag clearing into the arbitration loss handling logic. Signed-off-by: Jae Hyun Yoo

i2c: aspeed: filter garbage interrupts out

2021-10-19T22:10:32+00:00

AST2600 makes a garbage interrupt which is decribed as 'reserved' in datasheet so filter them out. Signed-off-by: Jae Hyun Yoo

Refine initialization flow in I2C driver

2021-10-19T22:10:32+00:00

Since we enabled I2C busses in u-boot, we need to disable the I2C bus and clear all garbage interrupts when kernel probes the bus. This commit refines the initialization flow by adding a bus reset at the beginning of probe function and by moving bus init function after interrupt handling setup. Signed-off-by: Jae Hyun Yoo

i2c: aspeed: add SLAVE_ADDR_RECEIVED_PENDING interrupt handling

2021-10-19T22:10:32+00:00

If a peer master sends messages too quickly before it processes previous slave DMA data handling, this indicator will be set. It's just a indicator and driver can't recover this case so just ignore it. Signed-off-by: Jae Hyun Yoo

i2c: aspeed: add H/W timeout support

2021-10-19T22:10:32+00:00

This commit adds I2C H/W timeout support. Signed-off-by: Jae Hyun Yoo

i2c: aspeed: add general call support

2021-10-19T22:10:32+00:00

This commit adds general call support into Aspeed I2C driver. This is downstream only customization so it should not go into upstream. Signed-off-by: Jae Hyun Yoo

i2c: aspeed: add DMA mode transfer support

2021-10-19T22:10:32+00:00

This commit adds DMA mode transfer support. Only AST2500 supports DMA mode under some limitations: I2C is sharing the DMA H/W with UHCI host controller and MCTP controller. Since those controllers operate with DMA mode only, I2C has to use buffer mode or byte mode instead if one of those controllers is enabled. Also make sure that if SD/eMMC or Port80 snoop uses DMA mode instead of PIO or FIFO respectively, I2C can't use DMA mode. Signed-off-by: Jae Hyun Yoo

i2c: aspeed: add buffer mode transfer support

2021-10-19T22:10:31+00:00

Byte mode currently this driver uses makes lots of interrupt call which isn't good for performance and it makes the driver very timing sensitive. To improve performance of the driver, this commit adds buffer mode transfer support which uses I2C SRAM buffer instead of using a single byte buffer. AST2400: It has 2 KBytes (256 Bytes x 8 pages) of I2C SRAM buffer pool from 0x1e78a800 to 0x1e78afff that can be used for all busses with buffer pool manipulation. To simplify implementation for supporting both AST2400 and AST2500, it assigns each 128 Bytes per bus without using buffer pool manipulation so total 1792 Bytes of I2C SRAM buffer will be used. AST2500: It has 16 Bytes of individual I2C SRAM buffer per each bus and its range is from 0x1e78a200 to 0x1e78a2df, so it doesn't have 'buffer page selection' bit field in the Function control register, and neither 'base address pointer' bit field in the Pool buffer control register it has. To simplify implementation for supporting both AST2400 and AST2500, it writes zeros on those register bit fields but it's okay because it does nothing in AST2500. It provides buffer based master and slave data transfer. Signed-off-by: Jae Hyun Yoo