BMC/Intel-BMC/linux.git/drivers/gpu/drm/msm/hdmi, branch dev-4.6

drm/msm: fix typo in the !COMMON_CLK case

2016-03-23T22:15:49+00:00

Signed-off-by: Rob Clark

drm/msm: rename hdmi symbols

2016-03-03T16:55:33+00:00

Global symbols in the kernel should be prefixed by the name of the subsystem and/or driver to avoid conflicts when all code is built-in. In this case, function names like 'hdmi_register' or 'hdmi_set_mode' are way too generic for an MSM specific DRM driver, so I'm renaming them all to msm_hdmi_* here. I also rename a lot of the 'static' symbols along with the global names for consistency, even though those are relatively harmless; they might only be slightly confusing when they show up in backtraces. Signed-off-by: Arnd Bergmann Signed-off-by: Rob Clark

drm/msm: update generated headers

2016-03-03T16:55:27+00:00

Pull in additional regs needed for a430, etc. Signed-off-by: Rob Clark

drm/msm/hdmi: HDMI 8996 PHY/PLL support

2016-02-29T14:48:32+00:00

Add support for the HDMI PHY/PLL found in MSM8996/APQ8096. Unlike the previous PHYs supported in the driver, this doesn't need the powerup/powerdown ops. The PLL prepare/unprepare clock ops enable/disable the phy itself. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/hdmi: Update generated headers for HDMI 8996 PHY

2016-02-29T14:48:31+00:00

Adds HDMI 8996 PHY offsets. The offsets are divided into 3 parts: - Core HDMI PHY registers - HDMI PLL registers (part of QSERDES block) - HDMI TX lane registers (part of QSERDES block) Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/hdmi: Update generated headers to split PHY/PLL offsets

2016-02-29T14:48:31+00:00

- Create separate domains for 8960 PHY and PLL - Create separate domains for 8x60 PHY Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/hdmi: Convert PHY files according to new design

2016-02-29T14:48:31+00:00

Remove the old PHY ops managed by hdmi_platform_config and use them as ops provided by the HDMI PHY driver. Remove the old HDMI 8960 PLL code that used the top level HDMI TX mmio base. NOTE: With this commit, HDMI functionality will break until the HDMI PHY/PLL register offsets in hdmi.xml.h aren't updated to be used as separate domains. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/hdmi: Make HDMI core get its PHY

2016-02-29T14:48:30+00:00

Make HDMI core get its PHY by parsing the "phys" phandle. The core will use this PHY reference to enable/disable PHY. The driver defers probe until PHY isn't available. The DT bindings used here is the same as the one used for PHYs using the common PHY framework bindings. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/hdmi: Manage HDMI PLL through PHY driver

2016-02-29T14:48:30+00:00

Add a helper to initialize PLL in the PHY driver. HDMI PLLs are going to have their own mmio base different from that of PHY. For the clock code in hdmi_phy_8960.c, some changes were needed for it to work with the updated register offsets. Create a copy of the updated clock code in hdmi_pll_8960.c, instead of rewriting it in hdmi_phy_8960.c itself. This removes the need to place CONFIG_COMMON_CLOCK checks all around, makes the code more legible, and also removes some old checkpatch warnings with the original code. The older hdmi pll clock ops in hdmi_phy_8960.c will be removed later. The driver will use these until the HDMI PHY/PLL register offsets aren't considered as separate domains (i.e. their offsets start from 0). Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/hdmi: Create a separate HDMI PHY driver

2016-02-29T14:48:30+00:00

Create a PHY device that represents the TX PHY and PLL parts of the HDMI block. This makes management of PHY specific resources (regulators and clocks) much easier, and makes the PHY and PLL usable independently. It also simplifies the core HDMI driver, which currently assigns phy ops among many other things. The PHY driver implementation done here is very similar to the PHY driver we already have for DSI. Keep the old hdmi_phy_funcs ops for now. The driver will use these until the HDMI PHY/PLL register offsets aren't considered as separate domains (i.e. their offsets start from 0). The driver doesn't use the common PHY framework for now. This is because it's hard to map our ops with the ops provided by the framework. The bindings used for this is the generic phy bindings. So, this can be adapted to the PHY framework in the future, if possible. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark