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<title>BMC/Intel-BMC/linux.git/drivers/gpu/drm/i915/intel_ringbuffer.c, branch dev-4.10</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.10</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.10'/>
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<updated>2017-01-18T14:31:11+00:00</updated>
<entry>
<title>drm/i915: Remove WaDisableLSQCROPERFforOCL KBL workaround.</title>
<updated>2017-01-18T14:31:11+00:00</updated>
<author>
<name>Francisco Jerez</name>
<email>currojerez@riseup.net</email>
</author>
<published>2017-01-12T10:44:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=4fc020d864647ea3ae8cb8f17d63e48e87ebd0bf'/>
<id>urn:sha1:4fc020d864647ea3ae8cb8f17d63e48e87ebd0bf</id>
<content type='text'>
The WaDisableLSQCROPERFforOCL workaround has the side effect of
disabling an L3SQ optimization that has huge performance implications
and is unlikely to be necessary for the correct functioning of usual
graphic workloads.  Userspace is free to re-enable the workaround on
demand, and is generally in a better position to determine whether the
workaround is necessary than the DRM is (e.g. only during the
execution of compute kernels that rely on both L3 fences and HDC R/W
requests).

The same workaround seems to apply to BDW (at least to production
stepping G1) and SKL as well (the internal workaround database claims
that it does for all steppings, while the BSpec workaround table only
mentions pre-production steppings), but the DRM doesn't do anything
beyond whitelisting the L3SQCREG4 register so userspace can enable it
when it sees fit.  Do the same on KBL platforms.

Improves performance of the GFXBench4 gl_manhattan31 benchmark by 60%,
and gl_4 (AKA car chase) by 14% on a KBL GT2 running Mesa master --
This is followed by a regression of 35% and 10% respectively for the
same benchmarks and platform caused by my recent patch series
switching userspace to use the dataport constant cache instead of the
sampler to implement uniform pull constant loads, which caused us to
hit more heavily the L3 cache (and on platforms other than KBL had the
opposite effect of improving performance of the same two benchmarks).
The overall effect on KBL of this change combined with the recent
userspace change is respectively 4.6% and 2.6%.  SynMark2 OglShMapPcf
was affected by the constant cache changes (though it improved as it
did on other platforms rather than regressing), but is not
significantly affected by this patch (with statistical significance of
5% and sample size 20).

v2: Drop some more code to avoid unused variable warning.

Fixes: 738fa1b3123f ("drm/i915/kbl: Add WaDisableLSQCROPERFforOCL")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99256
Signed-off-by: Francisco Jerez &lt;currojerez@riseup.net&gt;
Cc: Matthew Auld &lt;matthew.william.auld@gmail.com&gt;
Cc: Eero Tamminen &lt;eero.t.tamminen@intel.com&gt;
Cc: Jani Nikula &lt;jani.nikula@intel.com&gt;
Cc: Mika Kuoppala &lt;mika.kuoppala@intel.com&gt;
Cc: beignet@lists.freedesktop.org
Cc: &lt;stable@vger.kernel.org&gt; # v4.7+
Reviewed-by: Mika Kuoppala &lt;mika.kuoppala@intel.com&gt;
[Removed double Fixes tag]
Signed-off-by: Mika Kuoppala &lt;mika.kuoppala@intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/1484217894-20505-1-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 8726f2faa371514fba2f594d799db95203dfeee0)
Signed-off-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915: Defer transfer onto execution timeline to actual hw submission</title>
<updated>2016-11-14T21:00:23+00:00</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2016-11-14T20:40:59+00:00</published>
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<id>urn:sha1:d55ac5bf97c6b00539526e2aad8c938376681786</id>
<content type='text'>
Defer the transfer from the client's timeline onto the execution
timeline from the point of readiness to the point of actual submission.
For example, in execlists, a request is finally submitted to hardware
when the hardware is ready, and only put onto the hardware queue when
the request is ready. By deferring the transfer, we ensure that the
timeline is maintained in retirement order if we decide to queue the
requests onto the hardware in a different order than fifo.

v2: Rebased onto distinct global/user timeline lock classes.
v3: Play with the position of the spin_lock().
v4: Nesting finally resolved with distinct sw_fence lock classes.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Reviewed-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20161114204105.29171-4-chris@chris-wilson.co.uk
</content>
</entry>
<entry>
<title>drm/i915: Export a function to flush the context upon pinning</title>
<updated>2016-11-01T14:26:33+00:00</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2016-10-30T13:28:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=07c9a21a0d594c3acc0983e5e0a25d2364188d51'/>
<id>urn:sha1:07c9a21a0d594c3acc0983e5e0a25d2364188d51</id>
<content type='text'>
For legacy contexts we employ an optimisation to only flush the context
when binding into the global GTT. This avoids stalling on the GPU when
reloading an active context. Wrap this detail up into a helper and
export it for a potential third user. (Longer term, context pinning
needs to be reworked as the current handling of switch context pins too
late and so risks eviction and corrupting the request. Plans, plans,
plans.)

v2: Expand the comment explaining the optimisation for avoiding the
stall on active contexts.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20161030132820.32163-1-chris@chris-wilson.co.uk
Reviewed-by: Matthew Auld &lt;matthew.auld@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915: Move the global sync optimisation to the timeline</title>
<updated>2016-10-28T19:53:54+00:00</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2016-10-28T12:58:53+00:00</published>
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<id>urn:sha1:85e17f5974b357bc4a127be09de71b430be265e0</id>
<content type='text'>
Currently we try to reduce the number of synchronisations (now the
number of requests we need to wait upon) by noting that if we have
earlier waited upon a request, all subsequent requests in the timeline
will be after the wait. This only applies to requests in this timeline,
as other timelines will not be ordered by that waiter.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Reviewed-by: Joonas Lahtinen &lt;joonas.lahtinen@linux.intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-30-chris@chris-wilson.co.uk
</content>
</entry>
<entry>
<title>drm/i915: Defer breadcrumb emission</title>
<updated>2016-10-28T19:53:54+00:00</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2016-10-28T12:58:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=caddfe7192f5e74d65ebcfdae614f99e8fd87222'/>
<id>urn:sha1:caddfe7192f5e74d65ebcfdae614f99e8fd87222</id>
<content type='text'>
Move the actual emission of the breadcrumb for closing the request from
i915_add_request() to the submit callback. (It can be moved later when
required.) This allows us to defer the allocation of the global_seqno
from request construction to actual submission, allowing us to emit the
requests out of order (wrt to the order of their construction, they
still will only be executed one all of their dependencies are resolved
including that all earlier requests on their timeline have been
submitted.) We have to specialise how we then emit the request in order
to write into the preallocated space, rather than at the tail of the
ringbuffer (which will have been advanced by the addition of new
requests).

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Reviewed-by: Joonas Lahtinen &lt;joonas.lahtinen@linux.intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-29-chris@chris-wilson.co.uk
</content>
</entry>
<entry>
<title>drm/i915: Record space required for breadcrumb emission</title>
<updated>2016-10-28T19:53:53+00:00</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2016-10-28T12:58:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=98f29e8d908f2b9e3d966f6f7d63cd69b4aaf0a2'/>
<id>urn:sha1:98f29e8d908f2b9e3d966f6f7d63cd69b4aaf0a2</id>
<content type='text'>
In the next patch, we will use deferred breadcrumb emission. That requires
reserving sufficient space in the ringbuffer to emit the breadcrumb, which
first requires us to know how large the breadcrumb is.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Reviewed-by: Joonas Lahtinen &lt;joonas.lahtinen@linux.intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-28-chris@chris-wilson.co.uk
</content>
</entry>
<entry>
<title>drm/i915: Rename -&gt;emit_request to -&gt;emit_breadcrumb</title>
<updated>2016-10-28T19:53:53+00:00</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2016-10-28T12:58:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=9b81d556b11fe58827dcd87bc5deaf8da2f716ae'/>
<id>urn:sha1:9b81d556b11fe58827dcd87bc5deaf8da2f716ae</id>
<content type='text'>
Now that the emission of the request tail and its submission to hardware
are two separate steps, engine-&gt;emit_request() is confusing.
engine-&gt;emit_request() is called to emit the breadcrumb commands for the
request into the ring, name it such (engine-&gt;emit_breadcrumb).

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Reviewed-by: Joonas Lahtinen &lt;joonas.lahtinen@linux.intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-27-chris@chris-wilson.co.uk
</content>
</entry>
<entry>
<title>drm/i915: Introduce a global_seqno for each request</title>
<updated>2016-10-28T19:53:53+00:00</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2016-10-28T12:58:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=65e4760e3920c21073a9d737929dc36df561380f'/>
<id>urn:sha1:65e4760e3920c21073a9d737929dc36df561380f</id>
<content type='text'>
Though we will have multiple timelines, we still have a single timeline
of execution. This we can use to provide an execution and retirement order
of requests. This keeps tracking execution of requests simple, and vital
for preserving a single waiter (i.e. so that we can order the waiters so
that only the earliest to wakeup need be woken). To accomplish this we
distinguish the seqno used to order requests per-context (external) and
that used internally for execution.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Reviewed-by: Joonas Lahtinen &lt;joonas.lahtinen@linux.intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-26-chris@chris-wilson.co.uk
</content>
</entry>
<entry>
<title>drm/i915: Reuse the active golden render state batch</title>
<updated>2016-10-28T19:53:44+00:00</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2016-10-28T12:58:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=4e50f082ac51c95046a8315612ce1d9acb2b3d63'/>
<id>urn:sha1:4e50f082ac51c95046a8315612ce1d9acb2b3d63</id>
<content type='text'>
The golden render state is constant, but we recreate the batch setting
it up for every new context. If we keep that batch in a volatile cache
we can safely reuse it whenever we need to initialise a new context. We
mark the pages as purgeable and use the shrinker to recover pages from
the batch whenever we face memory pressues, recreating that batch afresh
on the next new context.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Reviewed-by: Joonas Lahtinen &lt;joonas.lahtien@linux.intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-8-chris@chris-wilson.co.uk
</content>
</entry>
<entry>
<title>drm/i915: Introduce an internal allocator for disposable private objects</title>
<updated>2016-10-28T19:53:44+00:00</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2016-10-28T12:58:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=920cf4194954ec6f971506013c7fe3b7def178b6'/>
<id>urn:sha1:920cf4194954ec6f971506013c7fe3b7def178b6</id>
<content type='text'>
Quite a few of our objects used for internal hardware programming do not
benefit from being swappable or from being zero initialised. As such
they do not benefit from using a shmemfs backing storage and since they
are internal and never directly exposed to the user, we do not need to
worry about providing a filp. For these we can use an
drm_i915_gem_object wrapper around a sg_table of plain struct page. They
are not swap backed and not automatically pinned. If they are reaped
by the shrinker, the pages are released and the contents discarded. For
the internal use case, this is fine as for example, ringbuffers are
pinned from being written by a request to be read by the hardware. Once
they are idle, they can be discarded entirely. As such they are a good
match for execlist ringbuffers and a small variety of other internal
objects.

In the first iteration, this is limited to the scratch batch buffers we
use (for command parsing and state initialisation).

v2: Allocate physically contiguous pages, where possible.
v3: Reduce maximum order on subsequent requests following an allocation
failure.
v4: Fix up mismatch between swiotlb segment size and page count (it
counts in 2k units, not 4k pages)

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Cc: Tvrtko Ursulin &lt;tvrtko.ursulin@linux.intel.com&gt;
Reviewed-by: Tvrtko Ursulin &lt;tvrtko.ursulin@linux.intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-7-chris@chris-wilson.co.uk
</content>
</entry>
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