<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/drivers/gpu/drm/amd/amdgpu/soc15.c, branch dev-5.2</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.2</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.2'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2019-08-29T06:30:22+00:00</updated>
<entry>
<title>drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possible</title>
<updated>2019-08-29T06:30:22+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-08-15T13:27:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=be85d2279c5c669f5b18e44951f2f6faf71922cf'/>
<id>urn:sha1:be85d2279c5c669f5b18e44951f2f6faf71922cf</id>
<content type='text'>
commit 98f58ada2d37e68125c056f1fc005748251879c2 upstream.

We need to set certain power gating flags after we determine
if the firmware version is sufficient to support gfxoff.
Previously we set the pg flags in early init, but we later
we might have disabled gfxoff if the firmware versions didn't
support it.  Move adding the additional pg flags after we
determine whether or not to support gfxoff.

Fixes: 005440066f92 ("drm/amdgpu: enable gfxoff again on raven series (v2)")
Tested-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Tested-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>drm/amdgpu/soc15: skip reset on init</title>
<updated>2019-05-20T17:48:43+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-05-17T14:21:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=5887a59961e2295c5b02f39dbc0ecf9212709b7b'/>
<id>urn:sha1:5887a59961e2295c5b02f39dbc0ecf9212709b7b</id>
<content type='text'>
Not necessary on soc15 and breaks driver reload on server cards.

Acked-by: Amber Lin &lt;Amber.Lin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: enable MGCG for PCO</title>
<updated>2019-04-19T16:33:15+00:00</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2019-04-19T07:12:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=fced5c70da82c94130948b6a3effcf292acc63fb'/>
<id>urn:sha1:fced5c70da82c94130948b6a3effcf292acc63fb</id>
<content type='text'>
Enable MGCG for picasso.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable Vega20 BACO reset support</title>
<updated>2019-04-19T16:32:08+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-04-15T04:07:28+00:00</published>
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<id>urn:sha1:017d75f1f96f5d969a04fafb1dcd617f9c27f21a</id>
<content type='text'>
PSP SOS firmware needs to be 0x80067 or later.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: error out on mode1 reset failure</title>
<updated>2019-03-28T03:40:12+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-03-15T02:02:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=39fee32b467c2773fdd71cb7cb2e0cdcb4104269'/>
<id>urn:sha1:39fee32b467c2773fdd71cb7cb2e0cdcb4104269</id>
<content type='text'>
The error return value should be correctly reflected.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: apply Vega20 BACO workaround</title>
<updated>2019-03-19T20:36:49+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-03-07T02:20:12+00:00</published>
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<id>urn:sha1:0c5ccf14f50431d0196b96025c878ae9f45676a9</id>
<content type='text'>
Applied vdci flush workaround for Vega20 BACO.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add limit of pp_feature for smu (v3)</title>
<updated>2019-03-19T20:04:02+00:00</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2019-01-31T06:11:04+00:00</published>
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<id>urn:sha1:3b94fb101f4071da2b555632d8d68a353a9dde79</id>
<content type='text'>
Move pp_feature from the struct of amd_powerplay to amdgpu_device.
Add pp_feature limit for overdrive interface.

v2: put pp_feature into struct amdgpu_pm.
v3: merge feature_mask with pp_feature.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Suggested-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Suggested-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: implement is_support_sw_smu function for new smu</title>
<updated>2019-03-19T20:03:57+00:00</updated>
<author>
<name>Kevin Wang</name>
<email>Kevin1.Wang@amd.com</email>
</author>
<published>2019-01-10T04:33:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=dc8e3a0c8efbaab9b4bc7b924463a56ea33d818c'/>
<id>urn:sha1:dc8e3a0c8efbaab9b4bc7b924463a56ea33d818c</id>
<content type='text'>
add this helper to check new sw-smu support.

Signed-off-by: Kevin Wang &lt;Kevin1.Wang@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable new smu ip block for vega20</title>
<updated>2019-03-19T20:03:54+00:00</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2018-11-29T10:46:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=2da5410bf4c974546f90c1262684f009c6f4a9da'/>
<id>urn:sha1:2da5410bf4c974546f90c1262684f009c6f4a9da</id>
<content type='text'>
Switch to new smu ip block since vega20.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use BACO on vega12 if platform supports it</title>
<updated>2019-03-05T20:09:33+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-02-11T02:50:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f8b18cf4c33452ee17936c63a0dea5278c4ac050'/>
<id>urn:sha1:f8b18cf4c33452ee17936c63a0dea5278c4ac050</id>
<content type='text'>
Use BACO for reset of the platform supports it.

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
