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<title>BMC/Intel-BMC/linux.git/drivers/gpio/Kconfig, branch dev-4.3</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.3</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.3'/>
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<updated>2015-12-14T05:54:25+00:00</updated>
<entry>
<title>drivers: Allow aspeed driver selection with COMPILE_TEST</title>
<updated>2015-12-14T05:54:25+00:00</updated>
<author>
<name>Andrew Jeffery</name>
<email>andrew@aj.id.au</email>
</author>
<published>2015-12-14T05:22:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=0f78ecd26f147632f170d155114b784e273eea3a'/>
<id>urn:sha1:0f78ecd26f147632f170d155114b784e273eea3a</id>
<content type='text'>
The patch doesn't fix PINCTRL_ASPEED as it's a not currently a useful
configuration option.

Signed-off-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
</content>
</entry>
<entry>
<title>gpio: Add Aspeed AST2400 driver</title>
<updated>2015-11-16T03:31:20+00:00</updated>
<author>
<name>Joel Stanley</name>
<email>joel@jms.id.au</email>
</author>
<published>2015-07-07T05:58:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=990ed34545c930d69885cb30087bbb16dbbb2563'/>
<id>urn:sha1:990ed34545c930d69885cb30087bbb16dbbb2563</id>
<content type='text'>
Fixes from Al:
 - Move aspeed Kconfig entry to correct menu. The Aspeed GPIO menu entry
   was added under "PCI GPIO expanders" which depends on PCI which may
   not be enabled for Aspeed. Move the entry to the "Memory mapped GPIO
   drivers" which describes the Aspeed GPIO driver more correctly.

Fixes from jk:
 - Pass struct resource directly to devm_ioremap_resource
 - Expose entire bank as one gpio chip
 - Implement interrupts for GPIO banks. We have a set of interrupt
   registers in each bank; this change adds a gpio irqchip to hook them
   up to the GPIO code.
 - Don't set names for aspeed GPIOs. We need the numbers for exporting anyway.
 - Constify the aspeed_gpio_banks structure

Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Alistair Popple &lt;alistair@popple.id.au&gt;
Signed-off-by: Jeremy Kerr &lt;jk@ozlabs.org&gt;
</content>
</entry>
<entry>
<title>gpio: rcar: GPIO_RCAR doesn't relate to ARM</title>
<updated>2015-09-14T07:12:03+00:00</updated>
<author>
<name>Kuninori Morimoto</name>
<email>kuninori.morimoto.gx@renesas.com</email>
</author>
<published>2015-08-25T09:12:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=aad38b75fb632200eb64282469458d21ce2cc39a'/>
<id>urn:sha1:aad38b75fb632200eb64282469458d21ce2cc39a</id>
<content type='text'>
8cd1470("gpio: rcar: Add r8a7795 (R-Car H3) support") added
GPIO support for r8a7795. r8a7795 based on CONFIG_ARM64.
OTOH, GPIO_RCAR driver can be compiled fine on non-ARM.
This patch removed ARM dependency for it.

Signed-off-by: Kuninori Morimoto &lt;kuninori.morimoto.gx@renesas.com&gt;
Acked-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Acked-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: brcmstb: Add interrupt and wakeup source support</title>
<updated>2015-08-13T11:13:26+00:00</updated>
<author>
<name>Gregory Fong</name>
<email>gregory.0xf0@gmail.com</email>
</author>
<published>2015-08-01T01:17:43+00:00</published>
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<id>urn:sha1:19a7b6940b781256ea8821e803d1e5f2933224b1</id>
<content type='text'>
Uses the gpiolib irqchip helpers.  For this to work, the irq setup
function is called once per bank instead of once per device.  Note
that all known uses of this block have a BCM7120 L2 interrupt
controller as a parent.  Supports interrupts for all GPIOs.

In the IRQ handler, we check for raised IRQs for invalid GPIOs and
warn (ratelimited) if they're encountered.

Also, several drivers (e.g. gpio-keys) allow for GPIOs to be
configured as wakeup sources, and this GPIO controller supports that
through a separate interrupt path.

The de-facto standard DT property "wakeup-source" is checked, since
that indicates whether the GPIO controller hardware can wake.  Uses
the IRQCHIP_MASK_ON_SUSPEND irq_chip flag because UPG GIO doesn't have
any of its own wakeup source configuration.

Aside regarding gpiolib irqchip helpers: It wasn't obvious (to me)
that you can have multiple chained irqchips and associated IRQ domains
for a single parent IRQ, and as long as the xlate function is written
correctly, a GPIO IRQ request end up checking the correct domain and
will get associated with the correct IRQ.  What helps make this clear
is to read
  drivers/gpio/gpiolib-of.c:
   - of_gpiochip_find_and_xlate()
   - of_get_named_gpiod_flags()
  drivers/gpio/gpiolib.c:
   - gpiochip_find()

Signed-off-by: Gregory Fong &lt;gregory.0xf0@gmail.com&gt;
Reviewed-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: etraxfs: add interrupt support</title>
<updated>2015-08-03T08:57:04+00:00</updated>
<author>
<name>Rabin Vincent</name>
<email>rabin@rab.in</email>
</author>
<published>2015-07-31T12:48:57+00:00</published>
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<id>urn:sha1:29b5357d25ba1528531ef9532b5743a32fdf8cd2</id>
<content type='text'>
On ETRAX FS, all pins on the first port (and only the first port) have
interrupt support.

On ARTPEC-3, all pins on all ports have interrupt support.  However,
there are only eight interrupts.  Each of the interrupts is associated
with a group of pins and for each interrupt the one pin from the group
which will trigger it can be selected.

Signed-off-by: Rabin Vincent &lt;rabin@rab.in&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: zx: Add ZTE zx296702 GPIO support</title>
<updated>2015-07-16T08:14:45+00:00</updated>
<author>
<name>Jun Nie</name>
<email>jun.nie@linaro.org</email>
</author>
<published>2015-06-29T02:35:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=e7aa6d8c1ba2429deef75fb24d029e00ab71bebf'/>
<id>urn:sha1:e7aa6d8c1ba2429deef75fb24d029e00ab71bebf</id>
<content type='text'>
Add ZTE zx296702 GPIO controller support

Signed-off-by: Jun Nie &lt;jun.nie@linaro.org&gt;
Acked-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: mvebu: kill bogus dependency on GPIO_GENERIC</title>
<updated>2015-07-15T22:11:03+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2015-06-19T11:31:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=4c52bd5c61118a47166ed5857f17698ce520b5fd'/>
<id>urn:sha1:4c52bd5c61118a47166ed5857f17698ce520b5fd</id>
<content type='text'>
The driver gpio-mvebu.c does not depend on gpio-generic.c at all.
Drop unneeded "select GPIO_GENERIC".

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: altera: kill bogus dependency on GPIO_GENERIC</title>
<updated>2015-07-15T22:11:02+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2015-06-19T11:31:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=d58ec58f40dc188fbb08edaa8c17840f71fe8a0e'/>
<id>urn:sha1:d58ec58f40dc188fbb08edaa8c17840f71fe8a0e</id>
<content type='text'>
The driver gpio-altera.c does not depend on gpio-generic.c at all.
Drop unneeded "select GPIO_GENERIC".

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Tien Hock Loh &lt;thloh@altera.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: Added support to Zynq Ultrascale+ MPSoC</title>
<updated>2015-06-10T07:44:17+00:00</updated>
<author>
<name>Anurag Kumar Vulisha</name>
<email>anurag.kumar.vulisha@xilinx.com</email>
</author>
<published>2015-06-04T12:10:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=bdf7a4ae371894b4dc10b5820006b0a82d484929'/>
<id>urn:sha1:bdf7a4ae371894b4dc10b5820006b0a82d484929</id>
<content type='text'>
Added support to Zynq Ultrascale+ MPSoC on the existing zynq
gpio driver.

Signed-off-by: Anurag Kumar Vulisha &lt;anuragku@xilinx.com&gt;
Acked-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: add ETRAXFS GPIO driver</title>
<updated>2015-06-10T07:11:10+00:00</updated>
<author>
<name>Rabin Vincent</name>
<email>rabin@rab.in</email>
</author>
<published>2015-06-06T20:30:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=d342571efea8135dcf0a96dcb9e54759adefdb27'/>
<id>urn:sha1:d342571efea8135dcf0a96dcb9e54759adefdb27</id>
<content type='text'>
Add a GPIO driver for the General I/O block on Axis ETRAX FS SoCs.

Signed-off-by: Rabin Vincent &lt;rabin@rab.in&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
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