BMC/Intel-BMC/linux.git/drivers/fsi/Makefile, branch dev-4.10

drivers: fsi: sbefifo: Add OCC driver

2017-06-05T08:06:32+00:00

This driver provides an atomic communications channel between the OCC on the POWER9 processor and a service processor (a BMC). The driver is dependent on the FSI SBEFIFO driver to get hardware access to the OCC SRAM. The format of the communication is a command followed by a response. Since the command and response must be performed atomically, the driver will perform this operations asynchronously. In this way, a write operation starts the command, and a read will gather the response data once it is complete. OpenBMC-Staging-Count: 1 Signed-off-by: Edward A. James Signed-off-by: Joel Stanley

drivers: fsi: Add FSI SBEFIFO driver

2017-06-01T04:58:20+00:00

IBM POWER9 processors contain some embedded hardware and software bits collectively referred to as the self boot engine (SBE). One role of the SBE is to act as a proxy that provides access to the registers of the POWER chip from other (embedded) systems. The POWER9 chip contains a hardware frontend for communicating with the SBE from remote systems called the SBEFIFO. The SBEFIFO logic is contained within an FSI CFAM (see Documentation/fsi) and as such the driver implements an FSI bus device. The SBE expects to communicate using a defined wire protocol; however, the driver knows nothing of the protocol and only provides raw access to the fifo device to userspace applications wishing to communicate with the SBE using the wire protocol. The SBEFIFO consists of two hardware fifos. The upstream fifo is used by the driver to transfer data to the SBE on the POWER chip, from the system hosting the driver. The downstream fifo is used by the driver to transfer data from the SBE on the power chip to the system hosting the driver. OpenBMC-Staging-Count: 1 Signed-off-by: Edward A. James Signed-off-by: Brad Bishop Signed-off-by: Joel Stanley

drivers/fsi: Add hub master support

2017-04-27T04:02:14+00:00

Add an engine driver to expose a "hub" FSI master - which has a set of control registers in the engine address space, and uses a chunk of the slave address space for actual FSI communication. Additional changes from Jeremy Kerr . OpenBMC-Staging-Count: 1 Signed-off-by: Chris Bostic Signed-off-by: Jeremy Kerr Signed-off-by: Joel Stanley

drivers/fsi: Add SCOM FSI client device driver

2017-04-27T04:02:14+00:00

Create a simple SCOM engine device driver that reads and writes its control registers via an FSI bus. Includes changes from Edward A. James . OpenBMC-Staging-Count: 1 Signed-off-by: Chris Bostic Signed-off-by: Edward A. James Signed-off-by: Jeremy Kerr Signed-off-by: Joel Stanley

drivers/fsi: Add GPIO based FSI master

2017-04-27T04:02:12+00:00

Implement a FSI master using GPIO. Will generate FSI protocol for read and write commands to particular addresses. Sends master command and waits for and decodes a slave response. Includes changes from Edward A. James and Jeremy Kerr . OpenBMC-Staging-Count: 1 Signed-off-by: Edward A. James Signed-off-by: Jeremy Kerr Signed-off-by: Chris Bostic Signed-off-by: Joel Stanley

drivers/fsi: Add empty fsi bus definitions

2017-04-27T04:01:40+00:00

This change adds the initial (empty) fsi bus definition, and introduces drivers/fsi/. Signed-off-by: Jeremy Kerr Signed-off-by: Chris Bostic Signed-off-by: Greg Kroah-Hartman (cherry picked from commit 0508ad1fff11a8b0acdf0333b5fe108d7bd5fce4) Signed-off-by: Joel Stanley