BMC/Intel-BMC/linux.git/drivers/crypto, branch v5.4.19Intel OpenBMC Linux kernel source tree (mirror)https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=v5.4.192020-02-11T12:35:31+00:00crypto: picoxcell - adjust the position of tasklet_init and fix missed tasklet_kill2020-02-11T12:35:31+00:00Chuhong Yuanhslester96@gmail.com2019-12-09T16:21:44+00:00urn:sha1:eee7a67c0391906f0e4ad51004ae861515c0e10c
commit 7f8c36fe9be46862c4f3c5302f769378028a34fa upstream.
Since tasklet is needed to be initialized before registering IRQ
handler, adjust the position of tasklet_init to fix the wrong order.
Besides, to fix the missed tasklet_kill, this patch adds a helper
function and uses devm_add_action to kill the tasklet automatically.
Fixes: ce92136843cb ("crypto: picoxcell - add support for the picoxcell crypto engines")
Signed-off-by: Chuhong Yuan <hslester96@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
crypto: atmel-aes - Fix counter overflow in CTR mode2020-02-11T12:35:31+00:00Tudor Ambarustudor.ambarus@microchip.com2019-12-05T09:54:01+00:00urn:sha1:12a15e1c544e22eafd83bbce5dcb5de7140a1e3b
commit 781a08d9740afa73357f1a60d45d7c93d7cca2dd upstream.
32 bit counter is not supported by neither of our AES IPs, all implement
a 16 bit block counter. Drop the 32 bit block counter logic.
Fixes: fcac83656a3e ("crypto: atmel-aes - fix the counter overflow in CTR mode")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
crypto: ccp - set max RSA modulus size for v3 platform devices as well2020-02-11T12:35:30+00:00Ard Biesheuvelardb@kernel.org2019-11-27T12:01:36+00:00urn:sha1:3a35871603a6a757af00a66abf2a7ca2d3199826
commit 11548f5a5747813ff84bed6f2ea01100053b0d8d upstream.
AMD Seattle incorporates a non-PCI version of the v3 CCP crypto
accelerator, and this version was left behind when the maximum
RSA modulus size was parameterized in order to support v5 hardware
which supports larger moduli than v3 hardware does. Due to this
oversight, RSA acceleration no longer works at all on these systems.
Fix this by setting the .rsamax property to the appropriate value
for v3 platform hardware.
Fixes: e28c190db66830c0 ("csrypto: ccp - Expand RSA support for a v5 ccp")
Cc: Gary R Hook <gary.hook@amd.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Gary R Hook <gary.hook@amd.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
crypto: hisilicon - Use the offset fields in sqe to avoid need to split scatterlists2020-02-11T12:35:30+00:00Jonathan CameronJonathan.Cameron@huawei.com2019-11-19T05:42:57+00:00urn:sha1:58d8f2dec6ab15bfa5ece28fc408afb06de9fb1a
commit 484a897ffa3005f16cd9a31efd747bcf8155826f upstream.
We can configure sgl offset fields in ZIP sqe to let ZIP engine read/write
sgl data with skipped data. Hence no need to splite the sgl.
Fixes: 62c455ca853e (crypto: hisilicon - add HiSilicon ZIP accelerator support)
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
crypto: ccree - fix PM race condition2020-02-11T12:35:22+00:00Gilad Ben-Yossefgilad@benyossef.com2020-01-16T10:14:43+00:00urn:sha1:5f63963669ec54ec5c36227e55f825f911bfaa90
commit 15fd2566bf54ee4d4781d8f170acfc9472a1541f upstream.
The PM code was racy, possibly causing the driver to submit
requests to a powered down device. Fix the race and while
at it simplify the PM code.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Fixes: 1358c13a48c4 ("crypto: ccree - fix resume race condition on init")
Cc: stable@kernel.org # v4.20
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
crypto: ccree - fix FDE descriptor sequence2020-02-11T12:35:22+00:00Ofir Drangofir.drang@arm.com2020-01-16T10:14:42+00:00urn:sha1:5e33535cf13c0a85f2bda324fced2502f9ca82e9
commit 5c83e8ec4d51ac4cc58482ed04297e6882b32a09 upstream.
In FDE mode (xts, essiv and bitlocker) the cryptocell hardware requires
that the the XEX key will be loaded after Key1.
Signed-off-by: Ofir Drang <ofir.drang@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
crypto: ccree - fix pm wrongful error reporting2020-02-11T12:35:22+00:00Gilad Ben-Yossefgilad@benyossef.com2020-01-16T10:14:40+00:00urn:sha1:d8760030e7017558faa748ba62376be5ab6babf1
commit cedca59fae5834af8445b403c66c9953754375d7 upstream.
pm_runtime_get_sync() can return 1 as a valid (none error) return
code. Treat it as such.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Cc: stable@vger.kernel.org # v4.19+
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
crypto: ccree - fix AEAD decrypt auth fail2020-02-11T12:35:22+00:00Gilad Ben-Yossefgilad@benyossef.com2020-01-16T10:14:38+00:00urn:sha1:70439e8b7ccfe70b810d98bb441c37e5c43ef8c1
commit 2a6bc713f1cef32e39e3c4e6f2e1a9849da6379c upstream.
On AEAD decryption authentication failure we are suppose to
zero out the output plaintext buffer. However, we've missed
skipping the optional associated data that may prefix the
ciphertext. This commit fixes this issue.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Fixes: e88b27c8eaa8 ("crypto: ccree - use std api sg_zero_buffer")
Cc: stable@vger.kernel.org
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
crypto: ccree - fix backlog memory leak2020-02-11T12:35:22+00:00Gilad Ben-Yossefgilad@benyossef.com2019-11-27T08:49:08+00:00urn:sha1:80c660892c24c867ee5b5bb367229ccfb2f2829b
commit 4df2ef25b3b3618fd708ab484fe6239abd130fec upstream.
Fix brown paper bag bug of not releasing backlog list item buffer
when backlog was consumed causing a memory leak when backlog is
used.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Cc: stable@vger.kernel.org # v4.19+
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
crypto: caam - do not reset pointer size from MCFGR register2020-02-01T09:34:52+00:00Iuliana Prodaniuliana.prodan@nxp.com2019-11-26T22:54:26+00:00urn:sha1:9f6d555f58f3fa3c610ec08b9bd5d6af7ad0592d
commit 7278fa25aa0ebcc0e62c39b12071069df13f7e77 upstream.
In commit 'a1cf573ee95 ("crypto: caam - select DMA address size at runtime")'
CAAM pointer size (caam_ptr_size) is changed from
sizeof(dma_addr_t) to runtime value computed from MCFGR register.
Therefore, do not reset MCFGR[PS].
Fixes: a1cf573ee95 ("crypto: caam - select DMA address size at runtime")
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Cc: <stable@vger.kernel.org>
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>