Intel OpenBMC Linux kernel source tree (mirror) https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.17 2018-02-22T02:44:36+00:00 2018-02-22T02:44:36+00:00 Rick Chen rickchen36@gmail.com 2017-12-12T05:12:21+00:00 urn:sha1:ea4625c3860ba002c83b1dffc528e1a4f0a89cf5 VDSO needs real-time cycle count to ensure the time accuracy. Unlike others, nds32 architecture does not define clock source, hence VDSO needs atcpit100 offering real-time cycle count to derive the correct time. Signed-off-by: Vincent Chen <vincentc@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> 2018-02-22T02:44:36+00:00 Rick Chen rickchen36@gmail.com 2017-12-11T07:53:15+00:00 urn:sha1:35dbb74aa752cff90e8dac1a24ed2a452aed0251 ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well. For system timer it will set channel 1 32-bit timer0 as clock source and count downwards until underflow and restart again. It also set channel 0 32-bit timer0 as clock event and count downwards until condition match. It will generate an interrupt for handling periodically. Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Add andestech atcpit100 timer