BMC/Intel-BMC/linux.git/drivers/clocksource/moxart_timer.c, branch dev-4.3

arm: Add Aspeed BMC machine

2015-11-16T03:31:15+00:00

Builds on Benh's initial bringup. - Fix reboot. aspeed_restart was declarted __init, so machine_restart was jumping into random memory. We can now reboot using the watchdog. - Add some device definitions - Use defines for aspeed machine - Add hpll to dts so drivers can query it - Build sram driver. We have a 32K chunk of SRAM on the AHB bus. Use the existing driver to provide access to the memory via genalloc. - Enable UART clock divisor. Our .dts assumes that the UART clock is divided by 13, but different u-boots may leave this bit in different states. Initialise it in aspeed_early_init explicitly. - Register APB clock with clk subsystem. This uses the fixed clock that Ben added to the device tree. It allows us to use the clock framework to query speeds from drivers. - irqchip/aspeed: Update to newer IRQ API - Use a common dtsi file for aspeed devices. The dts files for palmetto and barreleye are mostly the same; use a dtsi file for the common chip parts, with the board-specific things in the per-platform files. * Add #address- & #size-cells properties to i2c. * Added i2c busses and devices * Update device tree for ncsi support Signed-off-by: Joel Stanley Signed-off-by: Jeremy Kerr

clockevents/drivers/moxart: Migrate to new 'set-state' interface

2015-08-10T09:40:32+00:00

Migrate moxart driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Cc: Jonas Jensen Signed-off-by: Viresh Kumar Signed-off-by: Daniel Lezcano

ARM: clocksource: moxart: Add bitops.h include

2013-07-31T23:13:34+00:00

bitops.h included implicitly, add #include Signed-off-by: Jonas Jensen Signed-off-by: Daniel Lezcano

ARM: clocksource: Add support for MOXA ART SoCs

2013-07-18T13:27:47+00:00

This patch adds an clocksource driver for the main timer(s) found on MOXA ART SoCs. The MOXA ART SoC provides three separate timers with individual count/load/match registers, two are used here: TIMER1: clockevents, used to support oneshot and periodic events TIMER2: set up as a free running counter, used as clocksource Timers are preconfigured by bootloader to count down and interrupt on match or zero. Count increments every APB clock cycle and is automatically reloaded when it reaches zero. Signed-off-by: Jonas Jensen Signed-off-by: Daniel Lezcano