BMC/Intel-BMC/linux.git/drivers/clk, branch dev-5.14-intel

enable AST2600 I3C

2021-10-19T22:10:33+00:00

This commit ports I3C related changes from Aspeed SDK v00.05.05. It also includes Vitor's I3C cdev implementation which isn't upstreamed yet so it should be refined later. Signed-off-by: Ryan Chen Signed-off-by: Vitor Soares Signed-off-by: Jae Hyun Yoo

Refine clock settings

2021-10-19T22:10:33+00:00

This commit refines clock settings with cherry picking the latest code from Aspeed SDK v00.05.05 Signed-off-by: Jae Hyun Yoo

ast2600: enable high speed uart in kernel.

2021-10-19T22:10:33+00:00

Tested: 1. Config baud rate to 921600 in BIOS setup page 2. BMC could change env variable "hostserialcfg" to 1. 3. BMC is force to reboot and SPA baud rate is changed to 921600 successfully. 4. It is same for back to 115200. Signed-off-by: Kuiying Wang

clk: ast2600: enable ESPICLK always

2021-10-19T22:10:32+00:00

To support continous eSPI H/W handshaking, this patch enables ESPICLK always so that there discontinuity of eSPI handshaking while boot BMC. Signed-off-by: Jae Hyun Yoo

Add high speed baud rate support for UART

2021-10-19T22:10:30+00:00

In order to support high speed baud rate(921600 bps), the default UART clock(24MHz) needs to be switched to 192MHz(from USB2.0 port1 PHY). Create a new 192M Hz clock and assign it to uart, based on uart clock source configuration in SCU4C. bootloader(u-boot) will set SCU4C based on the environment configuration Signed-off-by: Yong Li

Merge tag 'v5.14.6' into dev-5.14

2021-09-22T00:13:12+00:00

This is the 5.14.6 stable release

clk: at91: clk-generated: Limit the requested rate to our range

2021-09-18T11:43:33+00:00

[ Upstream commit af7651e67b9d5f7e63ea23b118e3672ac662244a ] On clk_generated_determine_rate(), the requested rate could be outside of clk's range. Limit the rate to the clock's range to not return an error. Fixes: df70aeef6083 ("clk: at91: add generated clock driver") Signed-off-by: Codrin Ciubotariu Link: https://lore.kernel.org/r/20210707131213.3283509-1-codrin.ciubotariu@microchip.com Acked-by: Nicolas Ferre Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates

2021-09-18T11:43:33+00:00

[ Upstream commit c16edf5ff8ece9c4135175da4103cee1bec360be ] 'clk_init_data' for gates is setting up 'CLK_IS_CRITICAL' flag for all of them. This was being doing because some drivers of this SoC might not be ready to use the clock and we don't wanted the kernel to disable them since default behaviour without clock driver was to set all gate bits to enabled state. After a bit more testing and checking driver code it is safe to remove this flag and just let the kernel to disable those gates that are not in use. No regressions seems to appear. Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC") Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210727055537.11785-1-sergio.paracuellos@gmail.com Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: imx8m: fix clock tree update of TF-A managed clocks

2021-09-18T11:43:32+00:00

[ Upstream commit d36207b848a6490e14664e2197a1c8ab51d8148e ] On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree. Since 936c383673b9 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY: echo 25000000 > userspace/set_freq imx8m-ddrc-devfreq 3d400000.memory-controller: failed to set dram_apb parent: -16 Fix this by adding a new i.MX composite flag for firmware managed clocks, which clears SET_PARENT_GATE. This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free. Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags") Signed-off-by: Ahmad Fatoum Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210810151432.9228-1-a.fatoum@pengutronix.de Signed-off-by: Abel Vesa Signed-off-by: Sasha Levin

clk: imx8mm: use correct mux type for clkout path

2021-09-18T11:43:31+00:00

[ Upstream commit 1822b4dedc4d8cab96fd1d87bf8ff98194e29d9b ] The mux in the clkout path needs the current selected parent to be enabled for the switch to work. Use the correct mux type to have the clk framework take care of this requirement. Fixes: c1ae5c6f789a ("clk: imx8mm: add clkout1/2 support") Signed-off-by: Lucas Stach Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210628211554.2510238-1-l.stach@pengutronix.de Signed-off-by: Abel Vesa Signed-off-by: Sasha Levin