<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/drivers/clk/tegra/Makefile, branch dev-4.6</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.6</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.6'/>
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<updated>2015-12-17T12:37:56+00:00</updated>
<entry>
<title>clk: tegra: Add support for Tegra210 clocks</title>
<updated>2015-12-17T12:37:56+00:00</updated>
<author>
<name>Rhyland Klein</name>
<email>rklein@nvidia.com</email>
</author>
<published>2015-06-18T21:28:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=6b301a059eb2ebed1b12a900e3b21a38e48dd410'/>
<id>urn:sha1:6b301a059eb2ebed1b12a900e3b21a38e48dd410</id>
<content type='text'>
Implement clock support for Tegra210.

Signed-off-by: Rhyland Klein &lt;rklein@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Add Tegra124 DFLL clocksource platform driver</title>
<updated>2015-07-16T08:39:45+00:00</updated>
<author>
<name>Tuomas Tynkkynen</name>
<email>ttynkkynen@nvidia.com</email>
</author>
<published>2015-05-13T14:58:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=62a8a094b0e1de782a1b3dcb5e42a7d44379e583'/>
<id>urn:sha1:62a8a094b0e1de782a1b3dcb5e42a7d44379e583</id>
<content type='text'>
Add basic platform driver support for the fast CPU cluster DFLL
clocksource found on Tegra124 SoCs. This small driver selects the
appropriate Tegra124-specific characterization data and integration
code. It relies on the DFLL common code to do most of the work.

Signed-off-by: Tuomas Tynkkynen &lt;ttynkkynen@nvidia.com&gt;
Signed-off-by: Mikko Perttunen &lt;mikko.perttunen@kapsi.fi&gt;
Acked-by: Michael Turquette &lt;mturquette@linaro.org&gt;
[treding@nvidia.com: move setup code into -&gt;probe()]
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Add library for the DFLL clock source (open-loop mode)</title>
<updated>2015-07-16T07:32:44+00:00</updated>
<author>
<name>Tuomas Tynkkynen</name>
<email>ttynkkynen@nvidia.com</email>
</author>
<published>2015-05-13T14:58:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=d8d7a08fa82ff7c241c74c2461f342c5685dda27'/>
<id>urn:sha1:d8d7a08fa82ff7c241c74c2461f342c5685dda27</id>
<content type='text'>
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is the intended primary clock source for the fast CPU cluster.

This code is very closely based on a patch by Paul Walmsley from
December (http://comments.gmane.org/gmane.linux.ports.tegra/15273),
which in turn comes from the internal driver by originally created
by Aleksandr Frid &lt;afrid@nvidia.com&gt;.

Subsequent patches will add support for closed loop mode and drivers
for the Tegra124 fast CPU cluster DFLL devices, which rely on this
code.

Signed-off-by: Paul Walmsley &lt;pwalmsley@nvidia.com&gt;
Signed-off-by: Tuomas Tynkkynen &lt;ttynkkynen@nvidia.com&gt;
Signed-off-by: Mikko Perttunen &lt;mikko.perttunen@kapsi.fi&gt;
Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Acked-by: Michael Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: EMC clock driver depends on EMC driver</title>
<updated>2015-05-13T13:17:13+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-01T07:10:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=31b52ba42d71e9ed8ee544e64c340ec6c571272f'/>
<id>urn:sha1:31b52ba42d71e9ed8ee544e64c340ec6c571272f</id>
<content type='text'>
The EMC clock driver uses symbols exported by the EMC driver, so it
needs the corresponding dependency to avoid build breakage.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Add EMC clock driver</title>
<updated>2015-05-13T13:17:11+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2015-03-12T14:48:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=2db04f16b589c6c96bd07df3f1ef8558bfdb6810'/>
<id>urn:sha1:2db04f16b589c6c96bd07df3f1ef8558bfdb6810</id>
<content type='text'>
The driver is currently only tested on Tegra124 Jetson TK1, but should
work with other Tegra124 boards, provided that correct EMC tables are
provided through the device tree. Older chip models have differing
timing change sequences, so they are not currently supported.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Tomeu Vizoso &lt;tomeu.vizoso@collabora.com&gt;
[treding@nvidia.com: use more consistent function names]
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: Add support for the Tegra132 CAR IP block</title>
<updated>2015-02-02T13:47:53+00:00</updated>
<author>
<name>Paul Walmsley</name>
<email>pwalmsley@nvidia.com</email>
</author>
<published>2014-12-16T20:38:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=08acae34e8dadaa8c3a0a432760555bba1db8bfb'/>
<id>urn:sha1:08acae34e8dadaa8c3a0a432760555bba1db8bfb</id>
<content type='text'>
Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This
patch mostly deals with the small differences.

Since Tegra132 contains many of the same PLL clock sources used on
Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when
the kernel is configured to include Tegra132 support.

This patch is based on several patches from others:

1. a  patch from Peter De Schrijver:

http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html

2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on
Tegra132"), and

3. a patch from Allen Martin ("clk: Enable tegra clock driver for
tegra132").

Signed-off-by: Paul Walmsley &lt;paul@pwsan.com&gt;
Signed-off-by: Paul Walmsley &lt;pwalmsley@nvidia.com&gt;
Cc: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Cc: Allen Martin &lt;amartin@nvidia.com&gt;
Cc: Prashant Gaikwad &lt;pgaikwad@nvidia.com&gt;
Cc: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Cc: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Cc: Alexandre Courbot &lt;gnurou@gmail.com&gt;
Cc: Bill Huang &lt;bilhuang@nvidia.com&gt;
Cc: Mike Turquette &lt;mturquette@linaro.org&gt;
Cc: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: tegra124: Add support for Tegra124 clocks</title>
<updated>2013-11-26T16:46:54+00:00</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2013-09-09T10:23:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=76da314df603a08ebc463853030752251b260ab8'/>
<id>urn:sha1:76da314df603a08ebc463853030752251b260ab8</id>
<content type='text'>
Implement clock support for Tegra124.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: introduce common gen4 super clock</title>
<updated>2013-11-26T16:46:50+00:00</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2013-09-03T12:46:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=a7c8485a0ebbdce303c6709e208bb4fd08aff8ad'/>
<id>urn:sha1:a7c8485a0ebbdce303c6709e208bb4fd08aff8ad</id>
<content type='text'>
Introduce a common function which performs super clock initialization for
Tegra114 and beyond.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: move PMC, fixed clocks to common files</title>
<updated>2013-11-26T16:46:49+00:00</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2013-10-15T14:19:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=de4f30fd8403cd67449fbb9dc06a3d898fb9f10c'/>
<id>urn:sha1:de4f30fd8403cd67449fbb9dc06a3d898fb9f10c</id>
<content type='text'>
Introduce new files for fixed and PMC clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
</content>
</entry>
<entry>
<title>clk: tegra: move periph clocks to common file</title>
<updated>2013-11-26T16:46:47+00:00</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2013-09-04T14:04:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8'/>
<id>urn:sha1:76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8</id>
<content type='text'>
Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
</content>
</entry>
</feed>
