BMC/Intel-BMC/linux.git/drivers/bus/ti-sysc.c, branch dev-5.2

bus: ti-sysc: Handle devices with no control registers

2019-05-02T13:29:46+00:00

Some interconnect target modules have no module control registers at all, such as d_can on am335x and am437x. The d_can register offset at 0 is CTL register with 0x401 as the default value. I guess I mistook the 0x401 value for a revision register as the value happens to look similar to what the revision registers typically have for other modules. To handle modules with no control registers, we need to improve the ti-sysc driver a bit to bail out with errors on no control registers, and then we can remove the bogus revision registers for d_can. Cc: Sebastian Andrzej Siewior Tested-by: Keerthy Signed-off-by: Tony Lindgren

bus: ti-sysc: Add generic enable/disable functions

2019-04-09T15:58:48+00:00

For non legacy cases, add generic sysc_enable_module() and sysc_disable_module() functions. Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren

bus: ti-sysc: Detect DMIC for debugging

2019-04-05T22:10:36+00:00

Detect DMIC to see what we have connected if config DEBUG is enabled. Signed-off-by: Tony Lindgren

bus: ti-sysc: Handle swsup idle mode quirks

2019-04-05T22:10:36+00:00

In preparation of dropping interconnect target module platform data in favor of devicetree based data, we must pass swsup idle quirks to the platform data functions. For now, let's only tag the UART modules with the SWSUP_SIDLE_ACT quirk. The other modules will get tagged with swsup quirks as we drop the platform data and test the changes. Signed-off-by: Tony Lindgren

bus: ti-sysc: Add quirk handling for external optional functional clock

2019-04-03T16:32:35+00:00

We cannot access mcpdm registers at all unless there is an optional pdmclk configured. As this is currently only needed for mcpdm, let's check for mcpdm in sysc_get_clocks(). If it turns out to be needed for other modules too, we can add more flags to the quirks table for this. Signed-off-by: Tony Lindgren

bus: ti-sysc: Add support for early quirks based on register address

2019-04-03T16:32:35+00:00

At least mcpdm needs an optional external clock enabled to function and this clock typically comes from the PMIC. We can detect mcpdm based on the interconnect target module address and set a quirk flag early. To do this, let's initialize the clocks a bit later and add a new function for sysc_init_early_quirks(). Note that we cannot yet enable the early quirks for mcpdm until the optional external clocks are handled in the in the following patch. Signed-off-by: Tony Lindgren

bus: ti-sysc: Move rstctrl reset to happen later

2019-04-03T16:32:35+00:00

We can do the rsstctrl a bit later, but need to deassert rstctrl reset before the clocks are enabled if asserted. Let's only init restctrl in sysc_init_resets() and do the reset later on just before we enable the device clocks. Signed-off-by: Tony Lindgren

bus: ti-sysc: Manage clocks for the interconnect target module in all cases

2019-04-03T16:32:35+00:00

We are currently not managing interconnect target module clocks in the for legacy platform data based case. This causes a problem for using the platform data based functions when dropping the platform data for the interconnect target module configuration. To avoid a situation where we need to populate the main and optional clocks also for the platform data based functions, let's just manage the clocks directly in ti-sysc driver. This means that until the interconnect target module confugration platform data is dropped our use count for clk_enable() will be 2 instead of 1. Signed-off-by: Tony Lindgren

bus: ti-sysc: Allocate mdata as needed and do platform data based init later

2019-04-03T16:32:34+00:00

The platform data based init functions typically reset the interconnect target module configure the registers. As we may need the interconnect target module specific quirks configured based on the revision register, we want to move the platform data based init to happen later. Let's allocate mdata as needed so it's available for sysc_legacy_init() that we call with module clocks enabled from sysc_init_module(). Signed-off-by: Tony Lindgren

bus: ti-sysc: Enable all clocks directly during init to read revision

2019-04-03T16:32:34+00:00

The first thing we want to do is just read the module revision register to be able to configure the module specific quirks and configure the module registers. As the interconnect target module may not yet be properly configured and may need a reset first, we don't want to use pm_runtime_get() at this point. To read the revision register, let's just enable the all the clocks for the interconnect target module during init even if the optional clocks are not needed. That way we can read the revision register to configure the quirks needed for PM runtime. Signed-off-by: Tony Lindgren