BMC/Intel-BMC/linux.git/drivers/bus/Kconfig, branch dev-5.7

bus: mhi: core: Add support for registering MHI controllers

2020-03-19T06:41:04+00:00

This commit adds support for registering MHI controller drivers with the MHI stack. MHI controller drivers manages the interaction with the MHI client devices such as the external modems and WiFi chipsets. They are also the MHI bus master in charge of managing the physical link between the host and client device. This is based on the patch submitted by Sujeev Dias: https://lkml.org/lkml/2018/7/9/987 Signed-off-by: Sujeev Dias Signed-off-by: Siddartha Mohanadoss [jhugo: added static config for controllers and fixed several bugs] Signed-off-by: Jeffrey Hugo [mani: removed DT dependency, splitted and cleaned up for upstream] Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200220095854.4804-3-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman

bus: tegra-aconnect: Remove PM_CLK dependency

2020-01-10T11:31:24+00:00

The ACONNECT bus driver does not use pm-clk interface anymore and hence the dependency can be removed from its Kconfig option. Fixes: 0d7dab926130 ("bus: tegra-aconnect: use devm_clk_*() helpers") Signed-off-by: Sameer Pujar Acked-by: Jon Hunter Signed-off-by: Thierry Reding

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2019-12-05T19:43:31+00:00

Pull ARM SoC driver updates from Olof Johansson: "Various driver updates for platforms: - A larger set of work on Tegra 2/3 around memory controller and regulator features, some fuse cleanups, etc.. - MMP platform drivers, in particular for USB PHY, and other smaller additions. - Samsung Exynos 5422 driver for DMC (dynamic memory configuration), and ASV (adaptive voltage), allowing the platform to run at more optimal operating points. - Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas - Clock/reset control driver for TI/OMAP - Meson-A1 reset controller support - Qualcomm sdm845 and sda845 SoC IDs for socinfo" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits) firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT soc: fsl: add RCPM driver dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver soc: mediatek: Refactor bus protection control soc: mediatek: Refactor sram control ...

bus: hisi_lpc: Expand build test coverage

2019-11-05T00:47:48+00:00

Currently the driver will only ever be built for ARM64 because it selects CONFIG_INDIRECT_PIO, which itself depends on ARM64. Expand build test coverage for the driver to other architectures by only selecting CONFIG_INDIRECT_PIO for ARM64, when we really want it. We don't include ALPHA, C6X, HEXAGON, and PARISC architectures as they don't define {read, write}sb. Signed-off-by: John Garry Signed-off-by: Wei Xu

counter: new TI eQEP driver

2019-10-17T20:53:49+00:00

This adds a new counter driver for the Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP) module. Only very basic functionality is currently implemented - only enough to be able to read the position. The actual device has many more features which can be added to the driver on an as-needed basis. It is not possible to read the QEPA/B signal values in hardware, so that feature is omitted. The TI_PWMSS kernel option is selected in Kconfig to enable the parent bus, which is needed for power management. Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron

bus/ti-pwmss: move TI PWMSS driver from PWM to bus subsystem

2019-10-17T20:17:42+00:00

The TI PWMSS driver is a simple bus driver for providing power power management for the PWM peripherals on TI AM33xx SoCs, namely eCAP, eHRPWM and eQEP. The eQEP is a counter rather than a PWM, so it does not make sense to have the bus driver in the PWM subsystem since the PWMSS is not exclusive to PWM devices. Signed-off-by: David Lechner Signed-off-by: Jonathan Cameron

bus: Add support for Moxtet bus

2019-08-14T13:30:35+00:00

On the Turris Mox router different modules can be connected to the main CPU board: currently a module with a SFP cage, a module with MiniPCIe connector, a PCIe pass-through MiniPCIe connector module, a 4-port switch module, an 8-port switch module, and a 4-port USB3 module. For example: [CPU]-[PCIe-pass-through]-[PCIe]-[8-port switch]-[8-port switch]-[SFP] Each of this modules has an input and output shift register, and these are connected via SPI to the CPU board. Via SPI we are able to discover which modules are connected, in which order, and we can also read some information about the modules (eg. their interrupt status), and configure them. From each module 8 bits can be read (of which low 4 bits identify the module) and 8 bits can be written. For example from the module with a SFP cage we can read the LOS, TX-FAULT and MOD-DEF0 signals, while we can write TX-DISABLE and RATE-SELECT signals. This driver creates a new bus type, called "moxtet". For each Mox module it finds via SPI, it creates a new device on the moxtet bus so that drivers can be written for them. It also implements a virtual interrupt controller for the modules which send their interrupt status over the SPI shift register. These modules do this in addition to sending their interrupt status via the shared interrupt line. When the shared interrupt is triggered, we read from the shift register and handle IRQs for all devices which are in interrupt. The topology of how Mox modules are connected can then be read by listing /sys/bus/moxtet/devices. Link: https://lore.kernel.org/r/20190812161118.21476-2-marek.behun@nic.cz Signed-off-by: Marek Behún Reviewed-by: Linus Walleij Signed-off-by: Arnd Bergmann

bus: add bus driver for accessing Allwinner A64 DE2

2018-06-28T08:20:19+00:00

The "Display Engine 2.0" (usually called DE2) on the Allwinner A64 SoC is different from the ones on other Allwinner SoCs. It requires a SRAM region to be claimed, otherwise all DE2 subblocks won't be accessible. Add a bus driver for the Allwinner A64 DE2 part which claims the SRAM region when probing. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard

HISI LPC: Stop using MFD APIs

2018-05-10T16:30:06+00:00

The MFD APIs should only be used by drivers in drivers/mfd. It is not worth splitting the driver to have separate parts in drivers/bus and drivers/mfd, so just drop MFD API usage. As a solution, we will use the platform device APIs directly to achieve the same as we had when using MFD APIs. Signed-off-by: John Garry Reviewed-by: Andy Shevchenko Signed-off-by: Wei Xu

HISI LPC: Add Kconfig MFD_CORE dependency

2018-04-26T14:53:23+00:00

For ACPI support of the HiSilicon LPC driver we depend on MFD_CORE config. Currently the HiSi LPC Kconfig entry does not define this dependency, so add it. The reason for depending on MFD_CORE in the driver is that we model the LPC host as an MFD, in that a platform device will be created for each device on the bus. We do this as we need to modify the resources of these derived platform devices, something which we should not do to the original devices created in the ACPI scan. Details in e0aa1563f894 ("HISI LPC: Add ACPI support"). Fixes: e0aa1563f894 ("HISI LPC: Add ACPI support") Reported-and-tested-by: Tan Xiaojun Signed-off-by: John Garry Signed-off-by: Arnd Bergmann