BMC/Intel-BMC/linux.git/arch, branch dev-5.14-intel

arm: dts: add vref and battery sensing properties into ADC nodes

2021-10-27T21:37:39+00:00

This commit adds 'aspeed,int-vref-microvolt' and 'aspeed,battery-sensing' properties into ADC nodes for Intel AST2600 BMC platforms. Signed-off-by: Jae Hyun Yoo

ARM: dts: add rtc-pch node into aspeed-bmc-intel-ast2xxx

2021-10-27T21:37:14+00:00

This commit adds rtc-pch node into aspeed-bmc-intel-ast2500 and aspeed-bmc-intel-ast2600 to enable PCH RTC driver. Signed-off-by: Jae Hyun Yoo

ARM: dts: update offset for sio_status

2021-10-19T22:10:40+00:00

update the correct offset value of sio_status register to 0x10C. Tested: sio_status register updated after core bios done signal sent from BIOS. before: cat /sys/devices/platform/ahb/ahb:apb/1e789000.lpc/1e789000.lpc: regs/sio_status 16 after: cat /sys/devices/platform/ahb/ahb:apb/1e789000.lpc/1e789000.lpc: regs/sio_status 17 before: devmem 0x1e78910c 0x00000100 after: devmem 0x1e78910c 0x00000111 Signed-off-by: Chalapathi Venkataramashetty Change-Id: I6849980649f3fe353d67e1d131163a6aed777d77

Flash layout change for SPDM's AFM

2021-10-19T22:10:39+00:00

This change adds the SPI region needed for AFM(Attestation Firmware Manifest) which is used by SPDM Requester in PFR RoT. The change realigns the remaining flash region and appends the 256KB AFM region to staging region and reserves 768KB region for PSU and HSBP firmware. Tested: BMC boot in non-PFR and PFR environment. Change-Id: I322eebbdbb5dcffbfc45b8b50650ba4aaa5af186 Signed-off-by: Vikram Bodireddy

Update I3C bus device list

2021-10-19T22:10:39+00:00

To support communication with NVDIMM controllers, add definitions for these I3C devices. Each bus now has two definitions for each DIMM slot. If populated with a DDR5 DIMM, the SPD Hub device will be used to gather temperature readings. If populated with an NVDIMM, we'll only need to talk to the controller sitting behind the hub (local device type 1011b), to read temperature and use the FW mailbox. This also removes some logic in the I3C driver which restricts use of certain addresses due to signal integrity paranoia. An NVDIMM controller in slot 6 of any bus is blocked by this logic, and unfortunately we don't have any control over the static address scheme used on the SPD bus, so the restriction must be removed. Tested: Probed I3C busses successfully with DIMMs installed in busses 0 and 1: $ gpioset $(gpiofind FM_SPD_SWITCH_CTRL_N)=1 $ echo 1e7a2000.i3c0 > /sys/bus/platform/drivers/dw-i3c-master/bind $ echo 1e7a3000.i3c1 > /sys/bus/platform/drivers/dw-i3c-master/bind $ ls /dev/i3c* /dev/i3c-0-3c000000000 /dev/i3c-0-3c000000001 /dev/i3c-0-3c000000002 /dev/i3c-0-3c000000003 /dev/i3c-0-3c000000004 /dev/i3c-0-3c000000005 /dev/i3c-0-3c000000006 /dev/i3c-0-3c000000007 /dev/i3c-0-3c000000008 /dev/i3c-0-3c000000009 /dev/i3c-0-3c00000000a /dev/i3c-0-3c00000000b /dev/i3c-0-3c00000000c /dev/i3c-0-3c00000000d /dev/i3c-0-3c00000000e /dev/i3c-1-3c000000000 /dev/i3c-1-3c000000001 /dev/i3c-1-3c000000002 /dev/i3c-1-3c000000003 /dev/i3c-1-3c000000004 /dev/i3c-1-3c000000005 /dev/i3c-1-3c000000006 /dev/i3c-1-3c000000007 /dev/i3c-1-3c000000008 /dev/i3c-1-3c000000009 /dev/i3c-1-3c00000000a /dev/i3c-1-3c00000000b /dev/i3c-1-3c00000000c /dev/i3c-1-3c00000000d /dev/i3c-1-3c00000000e Change-Id: I016450edad1ed4ec981500f04122976f1647b8ee Signed-off-by: Jonathan Doman

ARM: dts: add silicon_id misc node into aspeed-bmc-intel-ast2xxx

2021-10-19T22:10:38+00:00

This commit adds silicon_id sub-node into misc_control node. Signed-off-by: Jae Hyun Yoo Change-Id: I60c09b654ca8a8881e5df4be07f062280210e570

hwmon: (aspeed-pwm-tacho) Add pwm chip driver support

2021-10-19T22:10:37+00:00

This commit adds pwm chip driver support into aspeed-g6-pwm-tacho driver to enable beep speaker driver. The pwm chip driver cannot be added as a separate platform driver because it makes resource conflicts with existing pwm-tacho driver so it uses hacky tweak on the existing driver. Note: Do not try upstream this hacky implementation. Signed-off-by: Jae Hyun Yoo Change-Id: I22ad12be2ae3a061d7942fec813cdb11be321db7

soc: aspeed: Miscellaneous control interfaces

2021-10-19T22:10:37+00:00

The ASPEED BMC SoCs have many knobs and switches that are sometimes design-specific and often defy any approach to unify them under an existing subsystem. Add a driver to translate a devicetree table into sysfs entries to expose bits and fields for manipulation from userspace. This encompasses concepts from scratch registers to boolean conditions to enable or disable host interface features. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley Signed-off-by: Jae Hyun Yoo

Enable mailbox interrupts

2021-10-19T22:10:37+00:00

Support interrupt generation for both 16 and 32 mailbox registers. Tested: After applied this patch, write the mailbox registers from BIOS side, the misc manager can capture the new mailbox data. Signed-off-by: Yong Li

Add AST2500 eSPI driver

2021-10-19T22:10:36+00:00

When PCH works under eSPI mode, the PMC (Power Management Controller) in PCH is waiting for SUS_ACK from BMC after it alerts SUS_WARN. It is in dead loop if no SUS_ACK assert. This is the basic requirement for the BMC works as eSPI slave. Also for the host power on / off actions, from BMC side, the following VW (Virtual Wire) messages are done in firmware: 1. SLAVE_BOOT_LOAD_DONE / SLAVE_BOOT_LOAD_STATUS 2. SUS_ACK 3. OOB_RESET_ACK 4. HOST_RESET_ACK Also, it provides monitoring interface of PLTRST_N signal through /dev/espi-pltrstn Signed-off-by: Haiyue Wang Signed-off-by: Jae Hyun Yoo Signed-off-by: James Feist Signed-off-by: Vernon Mauery