BMC/Intel-BMC/linux.git/arch/xtensa/include/asm/vectors.h, branch dev

xtensa: nommu: fix load address definitions

2014-10-21T09:28:53+00:00

Change KERNELOFFSET, LOAD_MEMORY_ADDRESS and VIRTUAL_MEMORY_ADDRESS to be relative to the start of physical memory in noMMU configuration, as there's no uniform memory remapping to KSEG starting at 0xd0000000. Signed-off-by: Max Filippov

xtensa: fix warning '"CONFIG_OF" is not defined'

2014-01-19T15:29:13+00:00

The warning only shows up when building MMUv3 configuration with OF support disabled. Signed-off-by: Max Filippov

xtensa: remap io area defined in device tree

2014-01-14T20:25:14+00:00

Use the simple-bus node to discover the io area, and remap the cached and bypass io ranges. The parent-bus-address value of the first triplet in the "ranges" property is used. This value is rounded down to the nearest 256MB boundary. The length of the io area is fixed at 256MB; the "ranges" property length value is ignored. Other limitations: (1) only the first simple-bus node is considered, and (2) only the first triplet of the "ranges" property is considered. See ePAPR 1.1 §6.5 for the simple-bus node description, and §2.3.8 for the "ranges" property description. Signed-off-by: Baruch Siach Signed-off-by: Max Filippov

xtensa: avoid duplicate of IO range definitions

2014-01-14T20:21:24+00:00

Define IO addresses in a single place, to make it easier to change for non-standard memory maps. Signed-off-by: Baruch Siach Signed-off-by: Max Filippov

xtensa: clean up include/asm/vectors.h

2014-01-14T18:19:47+00:00

- drop unused PHYSICAL_MEMORY_ADDRESS and XC_PADDR - fix NMI_VECTOR_VADDR and INTLEVEL7_VECTOR_VADDR definitions: there should be no XCHAL_ prefix in them; - fix the following warning seen with gcc-4.8.1: arch/xtensa/include/asm/vectors.h:71:5: warning: "XCHAL_HAVE_VECBASE" is not defined [-Wundef] Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: add MMU v3 support

2013-05-09T08:07:09+00:00

MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB way 6: Way 6 (512 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0x00000000 0x00000000 0x01 0x03 RWX Bypass 0x20000000 0x20000000 0x01 0x03 RWX Bypass 0x40000000 0x40000000 0x01 0x03 RWX Bypass 0x60000000 0x60000000 0x01 0x03 RWX Bypass 0x80000000 0x80000000 0x01 0x03 RWX Bypass 0xa0000000 0xa0000000 0x01 0x03 RWX Bypass 0xc0000000 0xc0000000 0x01 0x03 RWX Bypass 0xe0000000 0xe0000000 0x01 0x03 RWX Bypass This patch adds remapping code at the reset vector or at the kernel _start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that reconfigures MMUv3 as MMUv2: Way 5 (128 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0xd0000000 0x00000000 0x01 0x07 RWX WB 0xd8000000 0x00000000 0x01 0x03 RWX Bypass Way 6 (256 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0xe0000000 0xf0000000 0x01 0x07 RWX WB 0xf0000000 0xf0000000 0x01 0x03 RWX Bypass Signed-off-by: Max Filippov Signed-off-by: Chris Zankel