BMC/Intel-BMC/linux.git/arch/x86/kernel/cpu/intel.c, branch dev-5.4

x86/cpu: Add a "tsx=" cmdline option with TSX disabled by default

2019-10-28T07:36:58+00:00

Add a kernel cmdline parameter "tsx" to control the Transactional Synchronization Extensions (TSX) feature. On CPUs that support TSX control, use "tsx=on|off" to enable or disable TSX. Not specifying this option is equivalent to "tsx=off". This is because on certain processors TSX may be used as a part of a speculative side channel attack. Carve out the TSX controlling functionality into a separate compilation unit because TSX is a CPU feature while the TSX async abort control machinery will go to cpu/bugs.c. [ bp: - Massage, shorten and clear the arg buffer. - Clarifications of the tsx= possible options - Josh. - Expand on TSX_CTRL availability - Pawan. ] Signed-off-by: Pawan Gupta Signed-off-by: Borislav Petkov Signed-off-by: Thomas Gleixner Reviewed-by: Josh Poimboeuf

x86/cpu: Update init data for new Airmont CPU model

2019-09-06T05:30:40+00:00

Update properties for newly added Airmont CPU variant. Signed-off-by: Rahul Tanwar Signed-off-by: Tony Luck Cc: Gayatri Kammela Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: https://lkml.kernel.org/r/20190905193020.14707-5-tony.luck@intel.com Signed-off-by: Ingo Molnar

Merge branch 'x86/cleanups' into x86/cpu, to pick up dependent changes

2019-09-06T05:30:23+00:00

Signed-off-by: Ingo Molnar

x86/intel: Aggregate microserver naming

2019-08-28T09:29:32+00:00

Currently big microservers have _XEON_D while small microservers have _X, Make it uniformly: _D. for i in `git grep -l "$INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*_$X\|XEON_D$"` do sed -i -e 's/$\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*ATOM.*\)_X/\1_D/g' \ -e 's/$\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*\)_XEON_D/\1_D/g' ${i} done Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Tony Luck Cc: x86@kernel.org Cc: Dave Hansen Cc: Thomas Gleixner Cc: Borislav Petkov Link: https://lkml.kernel.org/r/20190827195122.677152989@infradead.org

x86/intel: Aggregate big core graphics naming

2019-08-28T09:29:31+00:00

Currently big core clients with extra graphics on have: - _G - _GT3E Make it uniformly: _G for i in `git grep -l "$INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*_GT3E"` do sed -i -e 's/$\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*\)_GT3E/\1_G/g' ${i} done Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Tony Luck Cc: x86@kernel.org Cc: Dave Hansen Cc: Thomas Gleixner Cc: Borislav Petkov Link: https://lkml.kernel.org/r/20190827195122.622802314@infradead.org

x86/intel: Aggregate big core mobile naming

2019-08-28T09:29:31+00:00

Currently big core mobile chips have either: - _L - _ULT - _MOBILE Make it uniformly: _L. for i in `git grep -l "$INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*_$MOBILE\|ULT$"` do sed -i -e 's/$\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*\)_$MOBILE\|ULT$/\1_L/g' ${i} done Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Tony Luck Cc: x86@kernel.org Cc: Dave Hansen Cc: Borislav Petkov Cc: Thomas Gleixner Link: https://lkml.kernel.org/r/20190827195122.568978530@infradead.org

x86/intel: Aggregate big core client naming

2019-08-28T09:29:31+00:00

Currently the big core client models either have: - no OPTDIFF - _CORE - _DESKTOP Make it uniformly: 'no OPTDIFF'. for i in `git grep -l "$INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*_$CORE\|DESKTOP$"` do sed -i -e 's/$\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6$.*\)_$CORE\|DESKTOP$/\1/g' ${i} done Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Tony Luck Cc: x86@kernel.org Cc: Dave Hansen Cc: Borislav Petkov Cc: Thomas Gleixner Link: https://lkml.kernel.org/r/20190827195122.513945586@infradead.org

x86/cpu: Use constant definitions for CPU models

2019-08-17T08:34:09+00:00

Replace model numbers with their respective macro definitions when comparing CPU models. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar Signed-off-by: Borislav Petkov Cc: alan@linux.intel.com Cc: cheol.yong.kim@intel.com Cc: Hans de Goede Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: qi-ming.wu@intel.com Cc: "Rafael J. Wysocki" Cc: Ricardo Neri Cc: Thomas Gleixner Cc: Tony Luck Cc: x86-ml Link: https://lkml.kernel.org/r/f7a0e142faa953a53d5f81f78055e1b3c793b134.1565940653.git.rahul.tanwar@linux.intel.com

x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata

2019-06-28T05:20:48+00:00

Processors which have self-snooping capability can handle conflicting memory type across CPUs by snooping its own cache. However, there exists CPU models in which having conflicting memory types still leads to unpredictable behavior, machine check errors, or hangs. Clear this feature on affected CPUs to prevent its use. Suggested-by: Alan Cox Signed-off-by: Ricardo Neri Signed-off-by: Thomas Gleixner Cc: Borislav Petkov Cc: Tony Luck Cc: "H. Peter Anvin" Cc: Andy Shevchenko Cc: Andi Kleen Cc: Hans de Goede Cc: Greg Kroah-Hartman Cc: Jordan Borgner Cc: "Ravi V. Shankar" Cc: Mohammad Etemadi Cc: Ricardo Neri Cc: Andy Shevchenko Cc: Andi Kleen Cc: Peter Feiner Cc: "Rafael J. Wysocki" Link: https://lkml.kernel.org/r/1561689337-19390-2-git-send-email-ricardo.neri-calderon@linux.intel.com

PM / arch: x86: Rework the MSR_IA32_ENERGY_PERF_BIAS handling

2019-04-07T20:33:19+00:00

The current handling of MSR_IA32_ENERGY_PERF_BIAS in the kernel is problematic, because it may cause changes made by user space to that MSR (with the help of the x86_energy_perf_policy tool, for example) to be lost every time a CPU goes offline and then back online as well as during system-wide power management transitions into sleep states and back into the working state. The first problem is that if the current EPB value for a CPU going online is 0 ('performance'), the kernel will change it to 6 ('normal') regardless of whether or not this is the first bring-up of that CPU. That also happens during system-wide resume from sleep states (including, but not limited to, hibernation). However, the EPB may have been adjusted by user space this way and the kernel should not blindly override that setting. The second problem is that if the platform firmware resets the EPB values for any CPUs during system-wide resume from a sleep state, the kernel will not restore their previous EPB values that may have been set by user space before the preceding system-wide suspend transition. Again, that behavior may at least be confusing from the user space perspective. In order to address these issues, rework the handling of MSR_IA32_ENERGY_PERF_BIAS so that the EPB value is saved on CPU offline and restored on CPU online as well as (for the boot CPU) during the syscore stages of system-wide suspend and resume transitions, respectively. However, retain the policy by which the EPB is set to 6 ('normal') on the first bring-up of each CPU if its initial value is 0, based on the observation that 0 may mean 'not initialized' just as well as 'performance' in that case. While at it, move the MSR_IA32_ENERGY_PERF_BIAS handling code into a separate file and document it in Documentation/admin-guide. Fixes: abe48b108247 (x86, intel, power: Initialize MSR_IA32_ENERGY_PERF_BIAS) Fixes: b51ef52df71c (x86/cpu: Restore MSR_IA32_ENERGY_PERF_BIAS after resume) Reported-by: Thomas Renninger Signed-off-by: Rafael J. Wysocki Reviewed-by: Hannes Reinecke Acked-by: Borislav Petkov Acked-by: Thomas Gleixner