<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/x86/kernel/amd_nb.c, branch dev-5.2</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.2</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.2'/>
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<updated>2019-06-19T15:09:51+00:00</updated>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 477</title>
<updated>2019-06-19T15:09:51+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-06-04T08:11:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f9724741de5bcc2f788a1abfd104b162533c8f31'/>
<id>urn:sha1:f9724741de5bcc2f788a1abfd104b162533c8f31</id>
<content type='text'>
Based on 1 normalized pattern(s):

  subject to gplv2

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 1 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Enrico Weigelt &lt;info@metux.net&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081204.018005938@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>x86/amd_nb: Add PCI device IDs for family 17h, model 30h</title>
<updated>2018-11-07T20:36:09+00:00</updated>
<author>
<name>Woods, Brian</name>
<email>Brian.Woods@amd.com</email>
</author>
<published>2018-11-06T20:08:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=be3518a16ef270e3b030a6ae96055f83f51bd3dd'/>
<id>urn:sha1:be3518a16ef270e3b030a6ae96055f83f51bd3dd</id>
<content type='text'>
Add the PCI device IDs for family 17h model 30h, since they are needed
for accessing various registers via the data fabric/SMN interface.

Signed-off-by: Brian Woods &lt;brian.woods@amd.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
CC: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Clemens Ladisch &lt;clemens@ladisch.de&gt;
CC: Guenter Roeck &lt;linux@roeck-us.net&gt;
CC: "H. Peter Anvin" &lt;hpa@zytor.com&gt;
CC: Ingo Molnar &lt;mingo@redhat.com&gt;
CC: Jean Delvare &lt;jdelvare@suse.com&gt;
CC: Jia Zhang &lt;qianyue.zj@alibaba-inc.com&gt;
CC: &lt;linux-hwmon@vger.kernel.org&gt;
CC: &lt;linux-pci@vger.kernel.org&gt;
CC: Pu Wen &lt;puwen@hygon.cn&gt;
CC: Thomas Gleixner &lt;tglx@linutronix.de&gt;
CC: x86-ml &lt;x86@kernel.org&gt;
Link: http://lkml.kernel.org/r/20181106200754.60722-4-brian.woods@amd.com
</content>
</entry>
<entry>
<title>x86/amd_nb: Add support for newer PCI topologies</title>
<updated>2018-11-07T20:28:29+00:00</updated>
<author>
<name>Woods, Brian</name>
<email>Brian.Woods@amd.com</email>
</author>
<published>2018-11-06T20:08:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=556e4c62baffa71e2045a298379db7e57dd47f3d'/>
<id>urn:sha1:556e4c62baffa71e2045a298379db7e57dd47f3d</id>
<content type='text'>
Add support for new processors which have multiple PCI root complexes
per data fabric/system management network interface.  If there are (N)
multiple PCI roots per DF/SMN interface, then the PCI roots are
redundant (as far as SMN/DF access goes).  For each DF/SMN interface:
map to the first available PCI root and skip the next N-1 PCI roots so
the following DF/SMN interface get mapped to a correct PCI root.

Ex:
DF/SMN 0 -&gt; 60
	    40
	    20
	    00
DF/SMN 1 -&gt; e0
	    c0
	    a0
	    80

Signed-off-by: Brian Woods &lt;brian.woods@amd.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
CC: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Clemens Ladisch &lt;clemens@ladisch.de&gt;
CC: Guenter Roeck &lt;linux@roeck-us.net&gt;
CC: "H. Peter Anvin" &lt;hpa@zytor.com&gt;
CC: Ingo Molnar &lt;mingo@redhat.com&gt;
CC: Jean Delvare &lt;jdelvare@suse.com&gt;
CC: Jia Zhang &lt;qianyue.zj@alibaba-inc.com&gt;
CC: &lt;linux-hwmon@vger.kernel.org&gt;
CC: &lt;linux-pci@vger.kernel.org&gt;
CC: Pu Wen &lt;puwen@hygon.cn&gt;
CC: Thomas Gleixner &lt;tglx@linutronix.de&gt;
CC: x86-ml &lt;x86@kernel.org&gt;
Link: http://lkml.kernel.org/r/20181106200754.60722-3-brian.woods@amd.com
</content>
</entry>
<entry>
<title>hwmon/k10temp, x86/amd_nb: Consolidate shared device IDs</title>
<updated>2018-11-07T20:28:04+00:00</updated>
<author>
<name>Woods, Brian</name>
<email>Brian.Woods@amd.com</email>
</author>
<published>2018-11-06T20:08:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=dedf7dce4cec5c0abe69f4fa6938d5100398220b'/>
<id>urn:sha1:dedf7dce4cec5c0abe69f4fa6938d5100398220b</id>
<content type='text'>
Consolidate shared PCI_DEVICE_IDs that were scattered through k10temp
and amd_nb, and move them into pci_ids.

Signed-off-by: Brian Woods &lt;brian.woods@amd.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Acked-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
CC: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Clemens Ladisch &lt;clemens@ladisch.de&gt;
CC: "H. Peter Anvin" &lt;hpa@zytor.com&gt;
CC: Ingo Molnar &lt;mingo@redhat.com&gt;
CC: Jean Delvare &lt;jdelvare@suse.com&gt;
CC: Jia Zhang &lt;qianyue.zj@alibaba-inc.com&gt;
CC: &lt;linux-hwmon@vger.kernel.org&gt;
CC: &lt;linux-pci@vger.kernel.org&gt;
CC: Pu Wen &lt;puwen@hygon.cn&gt;
CC: Thomas Gleixner &lt;tglx@linutronix.de&gt;
CC: x86-ml &lt;x86@kernel.org&gt;
Link: http://lkml.kernel.org/r/20181106200754.60722-2-brian.woods@amd.com
</content>
</entry>
<entry>
<title>x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge</title>
<updated>2018-09-27T16:28:58+00:00</updated>
<author>
<name>Pu Wen</name>
<email>puwen@hygon.cn</email>
</author>
<published>2018-09-25T14:46:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=c6babb5806b77c6ca7078c3487bb0a29704a4e38'/>
<id>urn:sha1:c6babb5806b77c6ca7078c3487bb0a29704a4e38</id>
<content type='text'>
Hygon's PCI vendor ID is 0x1d94, and there are PCI devices
0x1450/0x1463/0x1464 for the host bridge on the Hygon Dhyana platform.
Add Hygon Dhyana support to the PCI and northbridge subsystems by using
the code path of AMD family 17h.

 [ bp: Massage commit message, sort local vars into reverse xmas tree
   order and move the amd_northbridges.num check up. ]

Signed-off-by: Pu Wen &lt;puwen@hygon.cn&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;	# pci_ids.h
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: x86@kernel.org
Cc: thomas.lendacky@amd.com
Cc: helgaas@kernel.org
Cc: linux-pci@vger.kernel.org
Link: https://lkml.kernel.org/r/5f8877bd413f2ea0833378dd5454df0720e1c0df.1537885177.git.puwen@hygon.cn
</content>
</entry>
<entry>
<title>x86/amd_nb: Check vendor in AMD-only functions</title>
<updated>2018-09-27T16:28:58+00:00</updated>
<author>
<name>Pu Wen</name>
<email>puwen@hygon.cn</email>
</author>
<published>2018-09-25T14:45:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=b7a5cb4f220e78490735b2b984ad29b7d8e612a9'/>
<id>urn:sha1:b7a5cb4f220e78490735b2b984ad29b7d8e612a9</id>
<content type='text'>
Exit early in functions which are meant to run on AMD only but which get
run on different vendor (VMs, etc).

 [ bp: rewrite commit message. ]

Signed-off-by: Pu Wen &lt;puwen@hygon.cn&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Cc: bhelgaas@google.com
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: x86@kernel.org
Cc: thomas.lendacky@amd.com
Cc: helgaas@kernel.org
Link: https://lkml.kernel.org/r/487d8078708baedaf63eb00a82251e228b58f1c2.1537885177.git.puwen@hygon.cn
</content>
</entry>
<entry>
<title>x86/amd_nb: Add support for Raven Ridge CPUs</title>
<updated>2018-05-13T16:00:27+00:00</updated>
<author>
<name>Guenter Roeck</name>
<email>linux@roeck-us.net</email>
</author>
<published>2018-05-04T20:01:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f9bc6b2dd9cf025f827f471769e1d88b527bfb91'/>
<id>urn:sha1:f9bc6b2dd9cf025f827f471769e1d88b527bfb91</id>
<content type='text'>
Add Raven Ridge root bridge and data fabric PCI IDs.
This is required for amd_pci_dev_to_node_id() and amd_smn_read().

Cc: stable@vger.kernel.org # v4.16+
Tested-by: Gabriel Craciunescu &lt;nix.or.die@gmail.com&gt;
Acked-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
</content>
</entry>
<entry>
<title>x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping</title>
<updated>2018-02-15T00:15:52+00:00</updated>
<author>
<name>Jia Zhang</name>
<email>qianyue.zj@alibaba-inc.com</email>
</author>
<published>2018-01-01T01:52:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=b399151cb48db30ad1e0e93dd40d68c6d007b637'/>
<id>urn:sha1:b399151cb48db30ad1e0e93dd40d68c6d007b637</id>
<content type='text'>
x86_mask is a confusing name which is hard to associate with the
processor's stepping.

Additionally, correct an indent issue in lib/cpu.c.

Signed-off-by: Jia Zhang &lt;qianyue.zj@alibaba-inc.com&gt;
[ Updated it to more recent kernels. ]
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: bp@alien8.de
Cc: tony.luck@intel.com
Link: http://lkml.kernel.org/r/1514771530-70829-1-git-send-email-qianyue.zj@alibaba-inc.com
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>x86/cpu/AMD: Apply the Erratum 688 fix when the BIOS doesn't</title>
<updated>2017-10-22T11:06:02+00:00</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2017-10-22T10:47:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=bfc1168de949cd3e9ca18c3480b5085deff1ea7c'/>
<id>urn:sha1:bfc1168de949cd3e9ca18c3480b5085deff1ea7c</id>
<content type='text'>
Some F14h machines have an erratum which, "under a highly specific
and detailed set of internal timing conditions" can lead to skipping
instructions and RIP corruption.

Add the fix for those machines when their BIOS doesn't apply it or
there simply isn't BIOS update for them.

Tested-by: &lt;mirh@protonmail.ch&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Cc: &lt;stable@vger.kernel.org&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Sherry Hurwitz &lt;sherry.hurwitz@amd.com&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Yazen Ghannam &lt;Yazen.Ghannam@amd.com&gt;
Link: http://lkml.kernel.org/r/20171022104731.28249-1-bp@alien8.de
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197285
[ Added pr_info() that we activated the workaround. ]
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>x86/amd_nb: Add SMN and Indirect Data Fabric access for AMD Fam17h</title>
<updated>2016-11-16T19:46:38+00:00</updated>
<author>
<name>Yazen Ghannam</name>
<email>Yazen.Ghannam@amd.com</email>
</author>
<published>2016-11-10T21:10:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=ddfe43cdc0da3189feac4bb9f0f818bef6d6e56e'/>
<id>urn:sha1:ddfe43cdc0da3189feac4bb9f0f818bef6d6e56e</id>
<content type='text'>
Some devices on Fam17h can only be accessed through the System Management
Network (SMN). The SMN is accessed by a pair of index/data registers in PCI
config space. Add a pair of functions to read from and write to the SMN.

The Data Fabric on Fam17h allows multiple devices to use the same register
space. The registers of a specific device are accessed indirectly using the
device's DF InstanceId. Currently, we only need to read from these devices,
so only define a read function for now.

Signed-off-by: Yazen Ghannam &lt;Yazen.Ghannam@amd.com&gt;
Cc: linux-edac &lt;linux-edac@vger.kernel.org&gt;
Cc: x86-ml &lt;x86@kernel.org&gt;
Link: http://lkml.kernel.org/r/1478812257-5424-5-git-send-email-Yazen.Ghannam@amd.com
[ Boris: make __amd_smn_rw() even more compact. ]
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;

</content>
</entry>
</feed>
