BMC/Intel-BMC/linux.git/arch/x86/include/asm/vmx.h, branch dev

KVM: VMX: Add PML support in VMX

2015-01-30T08:39:54+00:00

This patch adds PML support in VMX. A new module parameter 'enable_pml' is added to allow user to enable/disable it manually. Signed-off-by: Kai Huang Reviewed-by: Xiao Guangrong Signed-off-by: Paolo Bonzini

kvm: x86: handle XSAVES vmcs and vmexit

2014-12-05T12:57:33+00:00

Initialize the XSS exit bitmap. It is zero so there should be no XSAVES or XRSTORS exits. Signed-off-by: Wanpeng Li Reviewed-by: Radim Krčmář Signed-off-by: Paolo Bonzini

kvm: x86: Add kvm_x86_ops hook that enables XSAVES for guest

2014-12-05T12:57:16+00:00

Expose the XSAVES feature to the guest if the kvm_x86_ops say it is available. Signed-off-by: Wanpeng Li Signed-off-by: Paolo Bonzini

KVM: nVMX: Fix returned value of MSR_IA32_VMX_PROCBASED_CTLS

2014-06-19T10:52:12+00:00

SDM says bits 1, 4-6, 8, 13-16, and 26 have to be set. Signed-off-by: Jan Kiszka Signed-off-by: Paolo Bonzini

KVM: x86: Fix constant value of VM_{EXIT_SAVE,ENTRY_LOAD}_DEBUG_CONTROLS

2014-06-19T10:52:11+00:00

The spec says those controls are at bit position 2 - makes 4 as value. The impact of this mistake is effectively zero as we only use them to ensure that these features are set at position 2 (or, previously, 1) in MSR_IA32_VMX_{EXIT,ENTRY}_CTLS - which is and will be always true according to the spec. Signed-off-by: Jan Kiszka Signed-off-by: Paolo Bonzini

KVM: x86: Intel MPX vmx and msr handle

2014-02-24T11:14:00+00:00

From caddc009a6d2019034af8f2346b2fd37a81608d0 Mon Sep 17 00:00:00 2001 From: Liu Jinsong Date: Mon, 24 Feb 2014 18:11:11 +0800 Subject: [PATCH v5 1/3] KVM: x86: Intel MPX vmx and msr handle This patch handle vmx and msr of Intel MPX feature. Signed-off-by: Xudong Hao Signed-off-by: Liu Jinsong Signed-off-by: Paolo Bonzini

KVM: nVMX: Add support for activity state HLT

2013-12-12T09:49:56+00:00

We can easily emulate the HLT activity state for L1: If it decides that L2 shall be halted on entry, just invoke the normal emulation of halt after switching to L2. We do not depend on specific host features to provide this, so we can expose the capability unconditionally. Signed-off-by: Jan Kiszka Signed-off-by: Paolo Bonzini

nEPT: Nested INVEPT

2013-08-07T13:57:42+00:00

If we let L1 use EPT, we should probably also support the INVEPT instruction. In our current nested EPT implementation, when L1 changes its EPT table for L2 (i.e., EPT12), L0 modifies the shadow EPT table (EPT02), and in the course of this modification already calls INVEPT. But if last level of shadow page is unsync not all L1's changes to EPT12 are intercepted, which means roots need to be synced when L1 calls INVEPT. Global INVEPT should not be different since roots are synced by kvm_mmu_load() each time EPTP02 changes. Reviewed-by: Xiao Guangrong Signed-off-by: Nadav Har'El Signed-off-by: Jun Nakajima Signed-off-by: Xinhao Xu Signed-off-by: Yang Zhang Signed-off-by: Gleb Natapov Signed-off-by: Paolo Bonzini

KVM: nVMX: Shadow-vmcs control fields/bits

2013-04-22T07:51:09+00:00

Add definitions for all the vmcs control fields/bits required to enable vmcs-shadowing Signed-off-by: Abel Gordon Reviewed-by: Orit Wasserman Signed-off-by: Gleb Natapov

KVM: VMX: Check the posted interrupt capability

2013-04-16T19:32:40+00:00

Detect the posted interrupt feature. If it exists, then set it in vmcs_config. Signed-off-by: Yang Zhang Reviewed-by: Gleb Natapov Signed-off-by: Marcelo Tosatti