BMC/Intel-BMC/linux.git/arch/sparc/kernel/hvcalls.S, branch dev

sparc: perf: Add support M7 processor

2015-03-20T01:54:49+00:00

The M7 processor has a different hypervisor group id and different PCR fast trap values. PIC read/write functions and PCR bit fields are the same as the T4 so those are reused. Signed-off-by: David Ahern Acked-by: Bob Picco Signed-off-by: David S. Miller

sparc64: T5 PMU

2014-09-17T01:26:40+00:00

The T5 (niagara5) has different PCR related HV fast trap values and a new HV API Group. This patch utilizes these and shares when possible with niagara4. We use the same sparc_pmu niagara4_pmu. Should there be new effort to obtain the MCU perf statistics then this would have to be changed. Cc: sparclinux@vger.kernel.org Signed-off-by: Bob Picco Signed-off-by: David S. Miller

sparc64: Add hypervisor interfaces for SPARC-T4 perf counter access.

2012-08-19T06:03:53+00:00

Unlike for previous chips, access to the perf-counter control registers are all hyper-privileged. Therefore, access to them must go through a hypervisor interface. Signed-off-by: David S. Miller

sparc: Set reboot-cmd using reboot data hypervisor call if available.

2011-08-03T04:28:52+00:00

Signed-off-by: David S. Miller

sparc,sparc64: unify kernel/

2008-12-04T17:17:21+00:00

o Move all files from sparc64/kernel/ to sparc/kernel - rename as appropriate o Update sparc/Makefile to the changes o Update sparc/kernel/Makefile to include the sparc64 files NOTE: This commit changes link order on sparc64! Link order had to change for either of sparc32 and sparc64. And assuming sparc64 see more testing than sparc32 change link order on sparc64 where issues will be caught faster. Signed-off-by: Sam Ravnborg Signed-off-by: David S. Miller