<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/sparc/include/asm/spitfire.h, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2014-09-09T22:24:10+00:00</updated>
<entry>
<title>sparc64: correctly recognise M6 and M7 cpu type</title>
<updated>2014-09-09T22:24:10+00:00</updated>
<author>
<name>Allen Pais</name>
<email>allen.pais@oracle.com</email>
</author>
<published>2014-09-08T06:18:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=cadbb58039f7cab1def9c931012ab04c953a6997'/>
<id>urn:sha1:cadbb58039f7cab1def9c931012ab04c953a6997</id>
<content type='text'>
The following patch adds support for correctly
recognising M6 and M7 cpu type.

Signed-off-by: Allen Pais &lt;allen.pais@oracle.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc: drop use of extern for prototypes in arch/sparc/include/asm</title>
<updated>2014-05-19T02:01:29+00:00</updated>
<author>
<name>Sam Ravnborg</name>
<email>sam@ravnborg.org</email>
</author>
<published>2014-05-16T21:25:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f05a68653e56ca2f23bccf7e50be69486886f052'/>
<id>urn:sha1:f05a68653e56ca2f23bccf7e50be69486886f052</id>
<content type='text'>
Drop extern for all prototypes and adjust alignment of parameters
as required after the removal.
In a few rare cases adjust linelength to conform to maximum 80 chars,
and likewise in a few rare cases adjust alignment of parameters
to static functions.

Signed-off-by: Sam Ravnborg &lt;sam@ravnborg.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc64: correctly recognize SPARC64-X chips</title>
<updated>2013-03-11T12:06:27+00:00</updated>
<author>
<name>Allen Pais</name>
<email>allen.pais@oracle.com</email>
</author>
<published>2013-03-05T23:47:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=76950e6e54ccfc98a25b501dbb1bc879cce1aa29'/>
<id>urn:sha1:76950e6e54ccfc98a25b501dbb1bc879cce1aa29</id>
<content type='text'>
The following patch adds support for correctly
recognizing SPARC-X chips.

cpu : Unknown SUN4V CPU
fpu : Unknown SUN4V FPU
pmu : Unknown SUN4V PMU

Signed-off-by: Katayama Yoshihiro &lt;kata1@jp.fujitsu.com&gt;
Signed-off-by: Allen Pais &lt;allen.pais@oracle.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc64: Future proof Niagara cpu detection.</title>
<updated>2011-09-16T21:21:33+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2011-09-11T17:42:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=08cefa9fa7e5b3ddaefb8b7bfa408d148429c08d'/>
<id>urn:sha1:08cefa9fa7e5b3ddaefb8b7bfa408d148429c08d</id>
<content type='text'>
Recognize T4 and T5 chips.  Treating them both as "T2 plus other
stuff" should be extremely safe and make sure distributions will work
when those chips actually ship to customers.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc: Add T3 sun4v cpu type and hypervisor group defines.</title>
<updated>2011-07-28T03:43:51+00:00</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2011-07-28T03:42:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=15e3608d7c273947dbf2eadbcaa66e51143928fb'/>
<id>urn:sha1:15e3608d7c273947dbf2eadbcaa66e51143928fb</id>
<content type='text'>
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc: unify kernel/cpu</title>
<updated>2008-12-07T08:04:30+00:00</updated>
<author>
<name>Sam Ravnborg</name>
<email>sam@ravnborg.org</email>
</author>
<published>2008-12-07T08:04:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=d34dd82905fb8e1117b67ab6c32989f88cfa0ba8'/>
<id>urn:sha1:d34dd82905fb8e1117b67ab6c32989f88cfa0ba8</id>
<content type='text'>
o use cpu_32.c as base
o move all sparc64 definitions to the common cpu.c
o use ifdef for the parts that differs and use cpu_32 as base
o spitfire.h required a CONFIG_SPARC64 guard to fix build on 32 bit

Signed-off-by: Sam Ravnborg &lt;sam@ravnborg.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sparc, sparc64: use arch/sparc/include</title>
<updated>2008-07-27T21:00:59+00:00</updated>
<author>
<name>Sam Ravnborg</name>
<email>sam@ravnborg.org</email>
</author>
<published>2008-07-27T21:00:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=a439fe51a1f8eb087c22dd24d69cebae4a3addac'/>
<id>urn:sha1:a439fe51a1f8eb087c22dd24d69cebae4a3addac</id>
<content type='text'>
The majority of this patch was created by the following script:

***
ASM=arch/sparc/include/asm
mkdir -p $ASM
git mv include/asm-sparc64/ftrace.h $ASM
git rm include/asm-sparc64/*
git mv include/asm-sparc/* $ASM
sed -ie 's/asm-sparc64/asm/g' $ASM/*
sed -ie 's/asm-sparc/asm/g' $ASM/*
***

The rest was an update of the top-level Makefile to use sparc
for header files when sparc64 is being build.
And a small fixlet to pick up the correct unistd.h from
sparc64 code.

Signed-off-by: Sam Ravnborg &lt;sam@ravnborg.org&gt;
</content>
</entry>
</feed>
