<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/sh/mm/cache-sh5.c, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2010-11-01T19:38:34+00:00</updated>
<entry>
<title>tree-wide: fix comment/printk typos</title>
<updated>2010-11-01T19:38:34+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2010-11-01T19:38:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=b595076a180a56d1bb170e6eceda6eb9d76f4cd3'/>
<id>urn:sha1:b595076a180a56d1bb170e6eceda6eb9d76f4cd3</id>
<content type='text'>
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Jiri Kosina &lt;jkosina@suse.cz&gt;
</content>
</entry>
<entry>
<title>sh64: Fix up reworked cache op build.</title>
<updated>2009-11-12T08:03:28+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-11-12T08:03:28+00:00</published>
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<id>urn:sha1:3af539e59cf3213cbe31ce7008f1db51c52665ca</id>
<content type='text'>
This gets the build fixed up for the sh64 cache enabled case.
Disabling still needs further abstraction for independent I/D-cache
disabling.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>Revert "sh: Kill off now redundant local irq disabling."</title>
<updated>2009-09-01T12:12:55+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-09-01T12:12:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=983f4c514c4c9ddac1077a2c805fd16cbe3f7487'/>
<id>urn:sha1:983f4c514c4c9ddac1077a2c805fd16cbe3f7487</id>
<content type='text'>
This reverts commit 64a6d72213dd810dd55bd0a503c36150af41c3c3.

Unfortunately we can't use on_each_cpu() for all of the cache ops, as
some of them only require preempt disabling. This seems to be the same
issue that impacts the mips r4k caches, where this code was based on.
This fixes up a deadlock that showed up in some IRQ context cases.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Kill off now redundant local irq disabling.</title>
<updated>2009-08-21T09:21:07+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-21T09:21:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=64a6d72213dd810dd55bd0a503c36150af41c3c3'/>
<id>urn:sha1:64a6d72213dd810dd55bd0a503c36150af41c3c3</id>
<content type='text'>
on_each_cpu() takes care of IRQ and preempt handling, the localized
handling in each of the called functions can be killed off.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Make cache flushers SMP-aware.</title>
<updated>2009-08-21T08:23:14+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-21T08:23:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f26b2a562b46ab186c8383993ab1332673ac4a47'/>
<id>urn:sha1:f26b2a562b46ab186c8383993ab1332673ac4a47</id>
<content type='text'>
This does a bit of rework for making the cache flushers SMP-aware. The
function pointer-based flushers are renamed to local variants with the
exported interface being commonly implemented and wrapping as necessary.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh64: Kill off dead i/d-cache disabled bits.</title>
<updated>2009-08-15T17:15:50+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-15T17:15:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=8c41cdcaffb09dca8e6ad7d4d8f885e0b86b9002'/>
<id>urn:sha1:8c41cdcaffb09dca8e6ad7d4d8f885e0b86b9002</id>
<content type='text'>
These will be handled through the shared cache interface instead, and
they are presently undefined anyways.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Fix up the SH-5 build with caches enabled.</title>
<updated>2009-08-15T16:50:17+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-15T16:50:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=94ecd224c940830e2f2724c3860eb7fb74c15d31'/>
<id>urn:sha1:94ecd224c940830e2f2724c3860eb7fb74c15d31</id>
<content type='text'>
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Migrate SH-4 cacheflush ops to function pointers.</title>
<updated>2009-08-15T03:29:49+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-15T03:29:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=37443ef3f0406e855e169c87ae3f4ffb4b6ff635'/>
<id>urn:sha1:37443ef3f0406e855e169c87ae3f4ffb4b6ff635</id>
<content type='text'>
This paves the way for allowing individual CPUs to overload the
individual flushing routines that they care about without having to
depend on weak aliases. SH-4 is converted over initially, as it wires
up pretty much everything. The majority of the other CPUs will simply use
the default no-op implementation with their own region flushers wired up.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Kill off unused flush_icache_user_range().</title>
<updated>2009-08-15T02:38:05+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-15T02:38:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=916e97834e023f89b31f796b53cc9c7956e7fe17'/>
<id>urn:sha1:916e97834e023f89b31f796b53cc9c7956e7fe17</id>
<content type='text'>
We use flush_cache_page() outright in copy_to_user_page(), and nothing
else needs it, so just kill it off. SH-5 still defines its own version,
but that too will go away in the same fashion once it converts over.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Centralize the CPU cache initialization routines.</title>
<updated>2009-08-15T02:05:42+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-15T02:05:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=ecba1060583635ab55092072441ff903b5e9a659'/>
<id>urn:sha1:ecba1060583635ab55092072441ff903b5e9a659</id>
<content type='text'>
This provides a central point for CPU cache initialization routines.
This replaces the antiquated p3_cache_init() method, which the vast
majority of CPUs never cared about.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
</feed>
