BMC/Intel-BMC/linux.git/arch/riscv/kernel/smpboot.c, branch dev-5.2

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174

2019-05-30T18:26:41+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Reviewed-by: Kate Stewart Reviewed-by: Richard Fontana Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman

RISC-V: Support nr_cpus command line option.

2019-05-17T03:42:04+00:00

If nr_cpus command line option is set, maximum possible cpu should be set to that value. Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig Signed-off-by: Palmer Dabbelt

RISC-V: Implement nosmp commandline option.

2019-04-30T16:47:45+00:00

nosmp command line option sets max_cpus to zero. No secondary harts will boot if this is enabled. But present cpu mask will still point to all possible masks. Fix present cpu mask for nosmp usecase. Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig Signed-off-by: Palmer Dabbelt

RISC-V: Compare cpuid with NR_CPUS before mapping.

2019-03-04T18:40:39+00:00

We should never have a cpuid greater that NR_CPUS. Compare with NR_CPUS before creating the mapping between logical and physical CPU ids. This is also mandatory as NR_CPUS check is removed from riscv_of_processor_hartid. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Christoph Hellwig Signed-off-by: Palmer Dabbelt

RISC-V: Do not wait indefinitely in __cpu_up

2019-03-04T18:40:36+00:00

In SMP path, __cpu_up waits for other CPU to come online indefinitely. This is wrong as other CPU might be disabled in machine mode and possible CPU is set to the cpus present in DT. Introduce a completion variable and waits only for a second. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Christoph Hellwig Signed-off-by: Palmer Dabbelt

riscv: use for_each_of_cpu_node iterator

2019-02-11T23:35:52+00:00

Use the new for_each_of_cpu_node() helper to iterate over cpu nodes instead of open coding. Note that this will allow matching also on the node name instead of the (for FDT) deprecated device_type property. Signed-off-by: Johan Hovold Signed-off-by: Palmer Dabbelt

RISC-V: fix bad use of of_node_put

2019-01-23T20:56:19+00:00

of_find_node_by_type already calls of_node_put, don't call it again. Fixes: 94f9bf118f ("RISC-V: Fix of_node_* refcount") Signed-off-by: Andreas Schwab Reviewed-by: Atish Patra Signed-off-by: Palmer Dabbelt

RISC-V: Fix of_node_* refcount

2018-12-21T16:10:49+00:00

Fix of_node* refcount at various places by using of_node_put. Signed-off-by: Atish Patra Signed-off-by: Palmer Dabbelt

RISC-V: Use Linux logical CPU number instead of hartid

2018-10-23T00:03:37+00:00

Setup the cpu_logical_map during boot. Moreover, every SBI call and PLIC context are based on the physical hartid. Use the logical CPU to hartid mapping to pass correct hartid to respective functions. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Christoph Hellwig Signed-off-by: Palmer Dabbelt

RISC-V: Use WRITE_ONCE instead of direct access

2018-10-23T00:03:37+00:00

The secondary harts spin on couple of per cpu variables until both of these are non-zero so it's not necessary to have any ordering here. However, WRITE_ONCE should be used to avoid tearing. Signed-off-by: Atish Patra Reviewed-by: Christoph Hellwig Signed-off-by: Palmer Dabbelt