<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/powerpc/kernel/head_fsl_booke.S, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
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<updated>2014-09-22T08:11:31+00:00</updated>
<entry>
<title>powerpc/booke: Revert SPE/AltiVec common defines for interrupt numbers</title>
<updated>2014-09-22T08:11:31+00:00</updated>
<author>
<name>Mihai Caraman</name>
<email>mihai.caraman@freescale.com</email>
</author>
<published>2014-08-20T13:09:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=2b2695a8d85593ec0253f7fdbeea1e18f0f9e5e2'/>
<id>urn:sha1:2b2695a8d85593ec0253f7fdbeea1e18f0f9e5e2</id>
<content type='text'>
Book3E specification defines shared interrupt numbers for SPE and AltiVec
units. Still SPE is present in e200/e500v2 cores while AltiVec is present in
e6500 core. So we can currently decide at compile-time which unit to support
exclusively. As Alexander Graf suggested, this will improve code readability
especially in KVM.

Use distinct defines to identify SPE/AltiVec interrupt numbers, reverting
c58ce397 and 6b310fc5 patches that added common defines.

Signed-off-by: Mihai Caraman &lt;mihai.caraman@freescale.com&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>powerpc/booke: Restrict SPE exception handlers to e200/e500 cores</title>
<updated>2014-09-22T08:11:31+00:00</updated>
<author>
<name>Mihai Caraman</name>
<email>mihai.caraman@freescale.com</email>
</author>
<published>2014-08-20T13:09:03+00:00</published>
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<id>urn:sha1:3477e71d53197d7f1b6a1f7416f3c42ffec5f221</id>
<content type='text'>
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.

Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and __setup_cpu functions.

Signed-off-by: Mihai Caraman &lt;mihai.caraman@freescale.com&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>powerpc/fsl_booke: smp support for booting a relocatable kernel above 64M</title>
<updated>2014-01-09T23:52:18+00:00</updated>
<author>
<name>Kevin Hao</name>
<email>haokexin@gmail.com</email>
</author>
<published>2013-12-24T07:12:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=0be7d969b0efef085ed6497d462ba16a875ca737'/>
<id>urn:sha1:0be7d969b0efef085ed6497d462ba16a875ca737</id>
<content type='text'>
When booting above the 64M for a secondary cpu, we also face the
same issue as the boot cpu that the PAGE_OFFSET map two different
physical address for the init tlb and the final map. So we have to use
switch_to_as1/restore_to_as0 between the conversion of these two
maps. When restoring to as0 for a secondary cpu, we only need to
return to the caller. So add a new parameter for function
restore_to_as0 for this purpose.

Use LOAD_REG_ADDR_PIC to get the address of variables which may
be used before we set the final map in cams for the secondary cpu.
Move the setting of cams a bit earlier in order to avoid the
unnecessary using of LOAD_REG_ADDR_PIC.

Signed-off-by: Kevin Hao &lt;haokexin@gmail.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/fsl_booke: make sure PAGE_OFFSET map to memstart_addr for relocatable kernel</title>
<updated>2014-01-09T23:52:17+00:00</updated>
<author>
<name>Kevin Hao</name>
<email>haokexin@gmail.com</email>
</author>
<published>2013-12-24T07:12:10+00:00</published>
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<id>urn:sha1:7d2471f9fa85089beb1cb9436ffc28f9e11e518d</id>
<content type='text'>
This is always true for a non-relocatable kernel. Otherwise the kernel
would get stuck. But for a relocatable kernel, it seems a little
complicated. When booting a relocatable kernel, we just align the
kernel start addr to 64M and map the PAGE_OFFSET from there. The
relocation will base on this virtual address. But if this address
is not the same as the memstart_addr, we will have to change the
map of PAGE_OFFSET to the real memstart_addr and do another relocation
again.

Signed-off-by: Kevin Hao &lt;haokexin@gmail.com&gt;
[scottwood@freescale.com: make offset long and non-negative in simple case]
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/fsl_booke: set the tlb entry for the kernel address in AS1</title>
<updated>2014-01-09T23:52:16+00:00</updated>
<author>
<name>Kevin Hao</name>
<email>haokexin@gmail.com</email>
</author>
<published>2013-12-24T07:12:07+00:00</published>
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<id>urn:sha1:78a235efdc42ff363de81fdbc171385e8b86b69b</id>
<content type='text'>
We use the tlb1 entries to map low mem to the kernel space. In the
current code, it assumes that the first tlb entry would cover the
kernel image. But this is not true for some special cases, such as
when we run a relocatable kernel above the 64M or set
CONFIG_KERNEL_START above 64M. So we choose to switch to address
space 1 before setting these tlb entries.

Signed-off-by: Kevin Hao &lt;haokexin@gmail.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc: enable the relocatable support for the fsl booke 32bit kernel</title>
<updated>2014-01-09T23:52:16+00:00</updated>
<author>
<name>Kevin Hao</name>
<email>haokexin@gmail.com</email>
</author>
<published>2013-12-24T07:12:06+00:00</published>
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<id>urn:sha1:dd189692d40948d6445bbaeb8cb9bf9d15f54dc6</id>
<content type='text'>
This is based on the codes in the head_44x.S. The difference is that
the init tlb size we used is 64M. With this patch we can only load the
kernel at address between memstart_addr ~ memstart_addr + 64M. We will
fix this restriction in the following patches.

Signed-off-by: Kevin Hao &lt;haokexin@gmail.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/fsl_booke: introduce get_phys_addr function</title>
<updated>2014-01-09T23:52:15+00:00</updated>
<author>
<name>Kevin Hao</name>
<email>haokexin@gmail.com</email>
</author>
<published>2013-12-24T07:12:04+00:00</published>
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<id>urn:sha1:99739611e816716d912ae89a4354237fc39745a6</id>
<content type='text'>
Move the codes which translate a effective address to physical address
to a separate function. So it can be reused by other code.

Signed-off-by: Kevin Hao &lt;haokexin@gmail.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/fsl_booke: protect the access to MAS7</title>
<updated>2014-01-09T23:52:14+00:00</updated>
<author>
<name>Kevin Hao</name>
<email>haokexin@gmail.com</email>
</author>
<published>2013-12-24T07:12:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=7c732cba3d9312882e82d91d5948261dfd5c8fe6'/>
<id>urn:sha1:7c732cba3d9312882e82d91d5948261dfd5c8fe6</id>
<content type='text'>
The e500v1 doesn't implement the MAS7, so we should avoid to access
this register on that implementations. In the current kernel, the
access to MAS7 are protected by either CONFIG_PHYS_64BIT or
MMU_FTR_BIG_PHYS. Since some code are executed before the code
patching, we have to use CONFIG_PHYS_64BIT in these cases.

Signed-off-by: Kevin Hao &lt;haokexin@gmail.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/fsl-booke: Use common defines for SPE/FP interrupts numbers</title>
<updated>2013-10-16T23:49:44+00:00</updated>
<author>
<name>Mihai Caraman</name>
<email>mihai.caraman@freescale.com</email>
</author>
<published>2013-07-01T15:35:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=c58ce397a62ec14b7b06c407a4173ed667e20d5f'/>
<id>urn:sha1:c58ce397a62ec14b7b06c407a4173ed667e20d5f</id>
<content type='text'>
On Book3E some SPE/FP/AltiVec interrupts share the same number. Use
common defines to indentify these numbers.

Signed-off-by: Mihai Caraman &lt;mihai.caraman@freescale.com&gt;
[scottwood@freescale.com: fixed space-before-tab]
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc: Remove the empty giveup_fpu() function on 32bit kernel</title>
<updated>2013-08-14T04:59:50+00:00</updated>
<author>
<name>Kevin Hao</name>
<email>haokexin@gmail.com</email>
</author>
<published>2013-07-14T09:02:06+00:00</published>
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<id>urn:sha1:5f20be4478032eeba66abddc79eae3abea45c5c8</id>
<content type='text'>
Instead of implementing an empty giveup_fpu() function for each
32bit processor type, replace them with an unique empty inline
function.

Signed-off-by: Kevin Hao &lt;haokexin@gmail.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
</entry>
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