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<title>BMC/Intel-BMC/linux.git/arch/nds32/kernel/cacheinfo.c, branch dev-4.17</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.17</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.17'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2018-02-22T02:44:32+00:00</updated>
<entry>
<title>nds32: Cache and TLB routines</title>
<updated>2018-02-22T02:44:32+00:00</updated>
<author>
<name>Greentime Hu</name>
<email>greentime@andestech.com</email>
</author>
<published>2017-10-24T07:40:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=7de9cf474083bfbba469f72dc208f7b51747632d'/>
<id>urn:sha1:7de9cf474083bfbba469f72dc208f7b51747632d</id>
<content type='text'>
This patch contains cache and TLB maintenance functions.

Signed-off-by: Vincent Chen &lt;vincentc@andestech.com&gt;
Signed-off-by: Greentime Hu &lt;greentime@andestech.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
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