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<title>BMC/Intel-BMC/linux.git/arch/mips/oprofile/common.c, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
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<updated>2015-04-01T15:22:13+00:00</updated>
<entry>
<title>MIPS: Add R16000 detection</title>
<updated>2015-04-01T15:22:13+00:00</updated>
<author>
<name>Joshua Kinard</name>
<email>kumba@gentoo.org</email>
</author>
<published>2015-01-21T12:59:45+00:00</published>
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<id>urn:sha1:3057739138eb8fbaa5154b149a864f5218898c73</id>
<content type='text'>
This allows the kernel to correctly detect an R16000 MIPS CPU on systems that
have those.  Otherwise, such systems will detect the CPU as an R14000, due to
similarities in the CPU PRId value.

Signed-off-by: Joshua Kinard &lt;kumba@gentoo.org&gt;
Cc: Linux MIPS List &lt;linux-mips@linux-mips.org&gt;
Patchwork: https://patchwork.linux-mips.org/patch/9092/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: oprofile: Enable backtrace on timer-based profiling</title>
<updated>2014-11-24T06:45:31+00:00</updated>
<author>
<name>Aaro Koskinen</name>
<email>aaro.koskinen@nsn.com</email>
</author>
<published>2014-10-17T15:10:25+00:00</published>
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<id>urn:sha1:1b48142a809ee03f48979fad647245dbe0ce423a</id>
<content type='text'>
Allow unsupported CPU types to use backtrace with timer-based profiling.
Some CPUs (notably OCTEON) lack architecture-specific oprofile driver. In
such case oprofile can fallback to timer-based mode, and arch code can
still provide the backtrace functionality. So just set up the backtrace
hook always.

Signed-off-by: Aaro Koskinen &lt;aaro.koskinen@nsn.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8108/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Loongson-3: Add oprofile support</title>
<updated>2014-11-24T06:45:01+00:00</updated>
<author>
<name>Huacai Chen</name>
<email>chenhc@lemote.com</email>
</author>
<published>2014-11-04T06:15:07+00:00</published>
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<id>urn:sha1:89467e73d3881a470ce4ffdcba1d5a5ed618379a</id>
<content type='text'>
Loongson-3 has two groups of performance counters, they are 4 sub-
registers of CP0's REG25. This patch add oprofile support.

REG25, sel 0: Perf Control of group 0;
REG25, sel 1: Perf Counter of group 0;
REG25, sel 2: Perf Control of group 1;
REG25, sel 3: Perf Counter of group 1.

Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Cc: John Crispin &lt;john@phrozen.org&gt;
Cc: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang &lt;zhangfx@lemote.com&gt;
Cc: Zhangjin Wu &lt;wuzhangjin@gmail.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/8328/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Add support for the M5150 processor</title>
<updated>2014-03-26T22:09:22+00:00</updated>
<author>
<name>Leonid Yegoshin</name>
<email>Leonid.Yegoshin@imgtec.com</email>
</author>
<published>2014-03-04T13:34:43+00:00</published>
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<id>urn:sha1:f36c4720fca325579faddc880d4e178e4ccbda88</id>
<content type='text'>
The M5150 core is a 32-bit MIPS RISC which implements the
MIPS Architecture Release-5  in a 5-stage pipeline.
In addition, it includes the MIPS Architecture Virtualization Module
that enables virtualization of operating systems,
which provides a scalable, trusted, and secure execution environment.

Signed-off-by: Leonid Yegoshin &lt;Leonid.Yegoshin@imgtec.com&gt;
Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6596/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: OProfile: Add CPU_P5600 cases</title>
<updated>2014-03-26T22:09:12+00:00</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2014-01-22T16:19:41+00:00</published>
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<id>urn:sha1:8c7f6ba3427b2a70aac0016f959b6977c395e8cb</id>
<content type='text'>
Add a CPU_P5600 cpu type case in oprofile_arch_init() to use the MIPS
model, and in mipsxx_init() to set the cpu_type string to "mips/P5600".

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Reviewed-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Cc: Robert Richter &lt;rric@kernel.org&gt;
Cc: oprofile-list@lists.sf.net
Patchwork: https://patchwork.linux-mips.org/patch/6410/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Add 1074K CPU support explicitly.</title>
<updated>2014-03-06T20:25:21+00:00</updated>
<author>
<name>Steven J. Hill</name>
<email>Steven.Hill@imgtec.com</email>
</author>
<published>2014-01-17T21:03:50+00:00</published>
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<id>urn:sha1:442e14a2c55e55f208bf87e3686396b4ff17ebf6</id>
<content type='text'>
The 1074K is a multiprocessing coherent processing system (CPS) based
on modified 74K cores. This patch makes the 1074K an actual unique
CPU type, instead of a 74K derivative, which it is not.

Signed-off-by: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Reviewed-by: Leonid Yegoshin &lt;Leonid.Yegoshin@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6389/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Add support for interAptiv cores</title>
<updated>2014-01-22T19:19:01+00:00</updated>
<author>
<name>Leonid Yegoshin</name>
<email>Leonid.Yegoshin@imgtec.com</email>
</author>
<published>2013-11-27T10:07:53+00:00</published>
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<id>urn:sha1:26ab96dfa9f98d74ef38efbe830d356547a292c1</id>
<content type='text'>
The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit.

Signed-off-by: Leonid Yegoshin &lt;Leonid.Yegoshin@imgtec.com&gt;
Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Signed-off-by: John Crispin &lt;blogic@openwrt.org&gt;
Patchwork: http://patchwork.linux-mips.org/patch/6163/
</content>
</entry>
<entry>
<title>MIPS: Add support for the proAptiv cores</title>
<updated>2014-01-22T19:18:59+00:00</updated>
<author>
<name>Leonid Yegoshin</name>
<email>Leonid.Yegoshin@imgtec.com</email>
</author>
<published>2013-11-14T16:12:27+00:00</published>
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<id>urn:sha1:708ac4b8703ea3204eee7c1c00c29912468a759d</id>
<content type='text'>
The proAptiv Multiprocessing System is a power efficient multi-core
microprocessor for use in system-on-chip (SoC) applications.
The proAptiv Multiprocessing System combines a deep pipeline
with multi-issue out of order execution for improved computational
throughput. The proAptiv Multiprocessing System can contain one to
six MIPS32r3 proAptiv cores, system level coherence
manager with L2 cache, optional coherent I/O port, and optional
floating point unit.

Signed-off-by: Leonid Yegoshin &lt;Leonid.Yegoshin@imgtec.com&gt;
Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Signed-off-by: John Crispin &lt;blogic@openwrt.org&gt;
Patchwork: http://patchwork.linux-mips.org/patch/6134/
</content>
</entry>
<entry>
<title>MIPS: Optimize current_cpu_type() for better code.</title>
<updated>2013-09-17T16:50:53+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2013-09-17T08:25:47+00:00</published>
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<id>urn:sha1:69f24d1784b631b81a54eb57c49bf46536dd2382</id>
<content type='text'>
 o Move current_cpu_type() to a separate header file
 o #ifdefing on supported CPU types lets modern GCC know that certain
   code in callers may be discarded ideally turning current_cpu_type() into
   a function returning a constant.
 o Use current_cpu_type() rather than direct access to struct cpuinfo_mips.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5833/
</content>
</entry>
<entry>
<title>oprofilefs_create_...() do not need superblock argument</title>
<updated>2013-09-04T02:52:48+00:00</updated>
<author>
<name>Al Viro</name>
<email>viro@zeniv.linux.org.uk</email>
</author>
<published>2013-07-19T12:10:36+00:00</published>
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<id>urn:sha1:6af4ea0ba708172be8caf1ba5047b2b8a9d2fea3</id>
<content type='text'>
same story as with oprofilefs_mkdir()

Signed-off-by: Al Viro &lt;viro@zeniv.linux.org.uk&gt;
</content>
</entry>
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