<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/mips/mm/uasm.c, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2015-02-20T14:31:27+00:00</updated>
<entry>
<title>MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX</title>
<updated>2015-02-20T14:31:27+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2015-01-15T13:11:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=e3d0ead59f6c1167c817ea338dd9395d517940e1'/>
<id>urn:sha1:e3d0ead59f6c1167c817ea338dd9395d517940e1</id>
<content type='text'>
Make messages refer to all CN6XXX.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Signed-off-by: Aleksey Makarov &lt;aleksey.makarov@auriga.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8941/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: mm: uasm: Add signed 9-bit immediate related macros</title>
<updated>2015-02-16T10:01:25+00:00</updated>
<author>
<name>Leonid Yegoshin</name>
<email>Leonid.Yegoshin@imgtec.com</email>
</author>
<published>2014-11-18T16:24:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=51eec48e1252ea39d21b5206e4962f09f823a369'/>
<id>urn:sha1:51eec48e1252ea39d21b5206e4962f09f823a369</id>
<content type='text'>
MIPS R6 redefines several instructions and reduces the immediate
field to 9-bits so add related macros for the microassembler.

Signed-off-by: Leonid Yegoshin &lt;Leonid.Yegoshin@imgtec.com&gt;
Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Add MFHC0 and MTHC0 instructions to uasm.</title>
<updated>2014-11-24T21:47:31+00:00</updated>
<author>
<name>Steven J. Hill</name>
<email>Steven.Hill@imgtec.com</email>
</author>
<published>2014-11-13T15:52:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=e2965cd0003f222bd49f67907c2bc6ed691c6d20'/>
<id>urn:sha1:e2965cd0003f222bd49f67907c2bc6ed691c6d20</id>
<content type='text'>
New instructions for Extended Physical Addressing (XPA) functionality.

Signed-off-by: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8453/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add SLT uasm instruction</title>
<updated>2014-06-26T09:48:19+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2014-06-23T09:38:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=7682f9e81899f1f874bd565daa7fb0b20024ed80'/>
<id>urn:sha1:7682f9e81899f1f874bd565daa7fb0b20024ed80</id>
<content type='text'>
It will be used later on by bpf-jit

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/7120/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add s3s1s2 instruction builder</title>
<updated>2014-06-26T09:48:19+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2014-06-23T09:38:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=9d9873697e8b5aaf39ef1f96e57ab4fffb8f45ae'/>
<id>urn:sha1:9d9873697e8b5aaf39ef1f96e57ab4fffb8f45ae</id>
<content type='text'>
It will be used later on by the SLT instruction.

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7119/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add lb uasm instruction</title>
<updated>2014-05-30T14:10:19+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2014-04-16T12:49:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=8248881835da58fa075299926c2994d12b56895b'/>
<id>urn:sha1:8248881835da58fa075299926c2994d12b56895b</id>
<content type='text'>
It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add mflo uasm instruction</title>
<updated>2014-05-30T13:57:44+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2014-04-14T14:42:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=16d21a812f6bfcbfa84ccc19d38abe797c71b73e'/>
<id>urn:sha1:16d21a812f6bfcbfa84ccc19d38abe797c71b73e</id>
<content type='text'>
It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add mul uasm instruction</title>
<updated>2014-05-30T13:54:39+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2014-04-08T11:47:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=a8e897ad00d3cfd0ab9029978f0c3f8ecd6fba61'/>
<id>urn:sha1:a8e897ad00d3cfd0ab9029978f0c3f8ecd6fba61</id>
<content type='text'>
It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6736/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add lh uam instruction</title>
<updated>2014-05-30T13:54:38+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2014-04-08T11:47:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=d6b3314b49e12e8c349deb4ca28e7028db00728f'/>
<id>urn:sha1:d6b3314b49e12e8c349deb4ca28e7028db00728f</id>
<content type='text'>
It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6733/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add wsbh uasm instruction</title>
<updated>2014-05-30T13:54:38+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2014-04-08T11:47:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=ab9e4fa092db6c4beea8fde67261959520675456'/>
<id>urn:sha1:ab9e4fa092db6c4beea8fde67261959520675456</id>
<content type='text'>
It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6732/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
</feed>
