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<title>BMC/Intel-BMC/linux.git/arch/mips/mm/init.c, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
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<updated>2015-05-19T06:39:15+00:00</updated>
<entry>
<title>sched/preempt, mm/kmap, MIPS: Disable preemption in kmap_coherent() explicitly</title>
<updated>2015-05-19T06:39:15+00:00</updated>
<author>
<name>David Hildenbrand</name>
<email>dahi@linux.vnet.ibm.com</email>
</author>
<published>2015-05-11T15:52:10+00:00</published>
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<id>urn:sha1:ce01948eb85da733558fa77c2a554144a57ab0fb</id>
<content type='text'>
k(un)map_coherent relies on pagefault_disable() to also disable
preemption.

Let's make this explicit, to prepare for pagefault_disable() not
touching preemption anymore.

This patch is based on a patch by Yang Shi on the -rt tree:
"k{un}map_coherent are just called when cpu_has_dc_aliases == 1 with VIPT
cache. However, actually, the most modern MIPS processors have PIPT dcache
without dcache alias issue. In such case, k{un}map_atomic will be called
with preempt enabled."

Reviewed-and-tested-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: David Hildenbrand &lt;dahi@linux.vnet.ibm.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Cc: David.Laight@ACULAB.COM
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: airlied@linux.ie
Cc: akpm@linux-foundation.org
Cc: benh@kernel.crashing.org
Cc: bigeasy@linutronix.de
Cc: borntraeger@de.ibm.com
Cc: daniel.vetter@intel.com
Cc: heiko.carstens@de.ibm.com
Cc: herbert@gondor.apana.org.au
Cc: hocko@suse.cz
Cc: hughd@google.com
Cc: mst@redhat.com
Cc: paulus@samba.org
Cc: ralf@linux-mips.org
Cc: schwidefsky@de.ibm.com
Cc: yang.shi@windriver.com
Link: http://lkml.kernel.org/r/1431359540-32227-6-git-send-email-dahi@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Add support for XPA.</title>
<updated>2015-03-19T16:39:49+00:00</updated>
<author>
<name>Steven J. Hill</name>
<email>Steven.Hill@imgtec.com</email>
</author>
<published>2015-02-27T00:16:38+00:00</published>
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<id>urn:sha1:c5b367835cfc7a8ef53b9670a409ffcc95194344</id>
<content type='text'>
Add support for extended physical addressing (XPA) so that
32-bit platforms can access equal to or greater than 40 bits
of physical addresses.

NOTE:
      1) XPA and EVA are not the same and cannot be used
         simultaneously.
      2) If you configure your kernel for XPA, the PTEs
         and all address sizes become 64-bit.
      3) Your platform MUST have working HIGHMEM support.

Signed-off-by: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9355/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT</title>
<updated>2014-11-24T21:46:44+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2014-11-21T23:16:48+00:00</published>
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<id>urn:sha1:34adb28d500e644cc260da4ceb66ba6dc0beaf93</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>mm: export symbol dependencies of is_zero_pfn()</title>
<updated>2014-09-14T14:25:14+00:00</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ard.biesheuvel@linaro.org</email>
</author>
<published>2014-09-12T20:17:23+00:00</published>
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<id>urn:sha1:0b70068e47e8f0c813a902dc3d6def601fd15acb</id>
<content type='text'>
In order to make the static inline function is_zero_pfn() callable by
modules, export its symbol dependencies 'zero_pfn' and (for s390 and
mips) 'zero_page_mask'.

We need this for KVM, as CONFIG_KVM is a tristate for all supported
architectures except ARM and arm64, and testing a pfn whether it refers
to the zero page is required to correctly distinguish the zero page
from other special RAM ranges that may also have the PG_reserved bit
set, but need to be treated as MMIO memory.

Signed-off-by: Ard Biesheuvel &lt;ard.biesheuvel@linaro.org&gt;
Acked-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Initialise MAARs</title>
<updated>2014-08-01T22:06:46+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2014-07-14T09:32:15+00:00</published>
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<id>urn:sha1:ab9988a3dafb8c94c2a19637fb00f7d1db799347</id>
<content type='text'>
Add initialisation for Memory Accessibility Attribute Registers. Generic
code cannot know the platform-specific requirements with regards to
speculative accesses, so it simply calls a platform_maar_init function
which platforms with MAARs are expected to implement by calling the
provided write_maar_pair function &amp; returning the number of MAAR pairs
used. A weak default implementation will simply use no MAAR pairs. Any
present but unused MAAR pairs are then marked invalid, effectively
disabling them.

The end result of this patch is that MAARs are all marked invalid, until
platforms implement the platform_maar_init function.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7331/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into mips-for-linux-next</title>
<updated>2014-05-29T13:08:23+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2014-05-28T17:00:14+00:00</published>
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<id>urn:sha1:2e2d663d2dd64ffe9855be0b35aa221c9b8139f2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>MIPS: add kmap_noncoherent to wire a cached non-coherent TLB entry</title>
<updated>2014-05-28T15:20:14+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2014-03-03T12:08:40+00:00</published>
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<id>urn:sha1:e2a9e5ad719fb424ab3c30520733aa0e8fbcf1ce</id>
<content type='text'>
This is identical to kmap_coherent apart from the cache coherency
attribute used for the TLB entry, so kmap_coherent is abstracted to
kmap_prot which is then called for both kmap_coherent &amp;
kmap_noncoherent. This will be used by a subsequent patch.

Suggested-by: Leonid Yegoshin &lt;leonid.yegoshin@imgtec.com&gt;
Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: MT: Remove SMTC support</title>
<updated>2014-05-23T22:07:01+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2014-05-23T14:29:44+00:00</published>
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<id>urn:sha1:b633648c5ad3cfbda0b3daea50d2135d44899259</id>
<content type='text'>
Nobody is maintaining SMTC anymore and there also seems to be no userbase.
Which is a pity - the SMTC technology primarily developed by Kevin D.
Kissell &lt;kevink@paralogos.com&gt; is an ingenious demonstration for the MT
ASE's power and elegance.

Based on Markos Chandras &lt;Markos.Chandras@imgtec.com&gt; patch
https://patchwork.linux-mips.org/patch/6719/ which while very similar did
no longer apply cleanly when I tried to merge it plus some additional
post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to
merge once upon a time.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: mm: init: Add free_init_pages() callback for EVA</title>
<updated>2014-03-26T22:09:18+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2014-01-15T14:06:03+00:00</published>
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<id>urn:sha1:0893d3fb8d27320d4301f14a0b331df291a08044</id>
<content type='text'>
A core in EVA mode can have any possible segment mapping, so the
default free_initmem_default() function may not always work as expected.
Therefore, add a callback that platforms can use to free up the init section.

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: mm: Move UNIQUE_ENTRYHI macro to a header file</title>
<updated>2014-01-22T19:18:58+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2013-11-14T16:12:22+00:00</published>
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<id>urn:sha1:c01905eeee579db98dd6b39d3f41497065ecc273</id>
<content type='text'>
The UNIQUE_ENTRYHI definition was duplicated whenever there
was the need to flush the TLB entries. We move this common
definition to a header file.

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Signed-off-by: John Crispin &lt;blogic@openwrt.org&gt;
Patchwork: http://patchwork.linux-mips.org/patch/6129/
</content>
</entry>
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