BMC/Intel-BMC/linux.git/arch/mips/kernel/mips-cm.c, branch dev-4.6

MIPS: Fix misspellings in comments.

2016-04-03T10:32:09+00:00

Signed-off-by: Adam Buchbinder Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12617/ Signed-off-by: Ralf Baechle

MIPS: CM, CPC: Ensure core-other GCRs reflect the correct core

2015-11-11T07:35:18+00:00

Ensure the update to which core the core-other GCR regions reflect has taken place before any core-other GCRs are accessed by placing a memory barrier (sync instruction) between the write to the core-other registers and any such GCR accesses. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: Bjorn Helgaas Cc: linux-kernel@vger.kernel.org Cc: Markos Chandras Patchwork: https://patchwork.linux-mips.org/patch/11209/ Signed-off-by: Ralf Baechle

MIPS: CM: Introduce core-other locking functions

2015-11-11T07:35:14+00:00

Introduce mips_cm_lock_other & mips_cm_unlock_other, mirroring the existing CPC equivalents, in order to lock access from the current core to another via the core-other GCR region. This hasn't been required in the past but with CM3 the CPC starts using GCR_CL_OTHER rather than CPC_CL_OTHER and this will be required for safety. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hogan Cc: Markos Chandras Patchwork: https://patchwork.linux-mips.org/patch/11207/ Signed-off-by: Ralf Baechle

MIPS: Always read full 64 bit CM error GCRs for CM3

2015-10-26T08:49:47+00:00

CM3 has 64 bit GCR_ERROR_* registers, but the code in mips_cm_error_report was previously only reading 32 bits of it in MIPS32 kernels. Fix by splitting the reads for CM2 & CM3, and making use of the read64_ variants of the accessor function for CM3. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hogan Cc: Markos Chandras Patchwork: https://patchwork.linux-mips.org/patch/11189/ Signed-off-by: Ralf Baechle

MIPS: Avoid buffer overrun in mips_cm_error_report

2015-10-26T08:49:46+00:00

Commit 3885c2b463f6 ("MIPS: CM: Add support for reporting CM cache errors") added cases for decoding errors reported by CM3, but leaves the buf variable which is printed as a string uninitialised for cause values other than 1, 2 or 3. Fix by ensuring the buf variable is initialised to an empty string in such cases. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: Markos Chandras Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11187/ Signed-off-by: Ralf Baechle

MIPS: Don't read GCRs when a CM is not present

2015-10-26T08:49:46+00:00

Commit 3885c2b463f6 ("MIPS: CM: Add support for reporting CM cache errors") leads to Malta boards unconditionally reading CM GCRs upon bus errors, regardless of whether a CM is present. This is incorrect & will lead to further exceptions. Fix by moving the GCR reads to after the check for whether a CM is present. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: Markos Chandras Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11186/ Signed-off-by: Ralf Baechle

MIPS: CM: Add support for reporting CM cache errors

2015-08-26T13:23:15+00:00

The CM cache error reporting code is not Malta specific and as such it should live in the mips-cm.c file. Moreover, CM2 and CM3 differ in the way cache errors are being recorded to the registers so extend the previous code to add support for the CM3 as well. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10646/ Signed-off-by: Ralf Baechle

MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels.

2015-08-26T13:23:14+00:00

The CMGCRBase register (CP0, 15, 3) register is 64-bit on MIPS64 so we change its type to unsigned long. Signed-off-by: Markos Chandras Cc: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10644/ Signed-off-by: Ralf Baechle

MIPS: mips-cm: Extend CM accessors for 64-bit CPUs

2015-08-26T13:23:12+00:00

Previously, the CM accessors were only accessing CM registers as u32 types instead of using the native CM register with. However, newer CMs may actually be 64-bit on MIPS64 cores. Fortunately, current 64-bit CMs (CM3) hold all the useful configuration bits in the lower half of the 64-bit registers (at least most of them) so they can still be accessed using the current 32-bit accessors. Signed-off-by: Markos Chandras Cc: Thomas Gleixner Cc: Jason Cooper Cc: Andrew Bresticker Cc: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10707/ Signed-off-by: Ralf Baechle

MIPS: Add platform callback before initializing the L2 cache

2015-08-26T13:23:11+00:00

Allow platforms to perform platform-specific steps before configuring the L2 cache. This is necessary for platforms with CM3 since the L2 parameters no longer live in the Config2 register. Signed-off-by: Markos Chandras Cc: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10642/ Signed-off-by: Ralf Baechle