BMC/Intel-BMC/linux.git/arch/mips/include/asm/page.h, branch dev

MIPS: Remove prototype for copy_user_page

2015-04-02T11:54:18+00:00

MIPS architecture code does not provide copy_user_page, so it should not provide a prototype for it either. Signed-off-by: Guenter Roeck Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9266/ Signed-off-by: Ralf Baechle

MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT

2014-11-24T21:46:44+00:00

Signed-off-by: Ralf Baechle

MIPS: Fix a warning for virt_to_page

2014-08-26T00:27:47+00:00

Compiling mm/highmem.c gives a warning: passing argument 1 of 'virt_to_phys' makes pointer from integer without a cast Fixed by casting to void* Signed-off-by: Zubair Lutfullah Kakakhel Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7337/ Signed-off-by: Ralf Baechle

MIPS: Spelling s/confugrations/configurations/

2014-08-26T00:18:58+00:00

Signed-off-by: Geert Uytterhoeven Cc: Jiri Kosina Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7573/ Signed-off-by: Ralf Baechle

MIPS: asm: page: Allow __pa_symbol overrides

2014-03-26T22:09:18+00:00

This will allow platforms to use an alternative way to get the physical address of a symbol. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras

MIPS: Add support for FTLBs

2014-01-22T19:19:00+00:00

The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: James Hogan Reviewed-by: Paul Burton Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/6139/

Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"

2013-07-01T13:10:58+00:00

This reverts commit 3f4579252aa166641861a64f1c2883365ca126c2. It is invalid because the macros CAC_ADDR and UNCAC_ADDR have a kernel virtual address as an argument and also returns a kernel virtual address. Using and physical address PHYS_OFFSET is blatantly wrong for a macro common to multiple platforms. Signed-off-by: Leonid Yegoshin Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Cc: Florian Fainelli Patchwork: https://patchwork.linux-mips.org/patch/5528/ Signed-off-by: Ralf Baechle

MIPS: Rewrite pfn_valid to work in modules, too.

2013-05-19T07:56:58+00:00

This fixes: MODPOST 393 modules ERROR: "min_low_pfn" [arch/mips/kvm/kvm.ko] undefined! make[3]: *** [__modpost] Error 1 It would have been possible to just export min_low_pfn but in the end pfn_valid should return 1 for any pfn argument for which a struct page exists so using min_low_pfn was wrong anyway. Signed-off-by: Ralf Baechle

MIPS: Make virt_to_phys() work for all unmapped addresses.

2013-05-17T18:36:15+00:00

As reported: This problem was discovered when doing BGP traffic with the TCP MD5 option activated, where the following call chain caused a crash: * tcp_v4_rcv * tcp_v4_timewait_ack * tcp_v4_send_ack -> follow stack variable rep.th * tcp_v4_md5_hash_hdr * tcp_md5_hash_header * sg_init_one * sg_set_buf * virt_to_page I noticed that tcp_v4_send_reset uses a similar stack variable and also calls tcp_v4_md5_hash_hdr, so it has the same problem. The networking core can indirectly call virt_to_phys() on stack addresses, if this is done from PID 0, the stack will usually be in CKSEG0, so virt_to_phys() needs to work there as well Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: Jiang Liu Cc: eunb.song@samsung.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5220/ Signed-off-by: Ralf Baechle

Revert "MIPS: page.h: Provide more readable definition for PAGE_MASK."

2013-04-22T16:09:35+00:00

This reverts commit c17a6554782ad531f4713b33fd6339ba67ef6391. Manuel Lauss writes: lmo commit c17a6554 (MIPS: page.h: Provide more readable definition for PAGE_MASK) apparently breaks ioremap of 36-bit addresses on my Alchemy systems (PCI and PCMCIA) The reason is that in arch/mips/mm/ioremap.c line 157 (phys_addr &= PAGE_MASK) bits 32-35 are cut off. Seems the new PAGE_MASK is explicitly 32bit, or one could make it signed instead of unsigned long.