<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/mips/cavium-octeon/setup.c, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2015-04-01T15:21:58+00:00</updated>
<entry>
<title>MIPS: mark prom_free_prom_memory() everywhere with __init</title>
<updated>2015-04-01T15:21:58+00:00</updated>
<author>
<name>Aaro Koskinen</name>
<email>aaro.koskinen@iki.fi</email>
</author>
<published>2015-02-25T23:31:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=aa816c1b390aacb698dd6faf5a8cbffb5123c03a'/>
<id>urn:sha1:aa816c1b390aacb698dd6faf5a8cbffb5123c03a</id>
<content type='text'>
On OCTEON the function is non-trivial and we can potentially even save
some memory.

Signed-off-by: Aaro Koskinen &lt;aaro.koskinen@iki.fi&gt;
Acked-by: David Daney &lt;david.daney@cavium.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9338/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: OCTEON: Use correct CSR to soft reset</title>
<updated>2015-04-01T15:21:44+00:00</updated>
<author>
<name>Chandrakala Chavva</name>
<email>cchavva@caviumnetworks.com</email>
</author>
<published>2015-03-05T15:06:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=fe2360f8f505ea8340f710f1c80a8f56462bdd62'/>
<id>urn:sha1:fe2360f8f505ea8340f710f1c80a8f56462bdd62</id>
<content type='text'>
This fixes reboot for Octeon III boards

[ralf@linux-mips.org: Dropped segment for function cvmx_reset_octeon()
which was removed by the preceeding commit.]

Signed-off-by: Chandrakala Chavva &lt;cchavva@caviumnetworks.com&gt;
Signed-off-by: Aleksey Makarov &lt;aleksey.makarov@auriga.com&gt;
Cc: David Daney &lt;david.daney@cavium.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9464/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: OCTEON: Add semaphore to serialize bootbus accesses.</title>
<updated>2015-04-01T15:21:42+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2015-03-05T14:31:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=24d4e7f642882a8a13da170b4ba86eec8fa91bf2'/>
<id>urn:sha1:24d4e7f642882a8a13da170b4ba86eec8fa91bf2</id>
<content type='text'>
Some hardware blocks attached to the OCTEON bootbus run asynchronously
to accesses from the CPUs.  These include MMC/SD host, CF(when using
DMA), and NAND controller.  A bus error, or corrupt data may occur if
a CPU is trying to access a bootbus connected device at the same time
the bus is running asynchronous operations.

To work around these problems we add this semaphore that must be
acquired before initiating bootbus activity.  Subsequent patches will
add users for this.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
[aleksey.makarov@auriga.com: combine the patches]
Signed-off-by: Aleksey Makarov &lt;aleksey.makarov@auriga.com&gt;
Signed-off-by: Chandrakala Chavva &lt;cchavva@caviumnetworks.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9459/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: OCTEON: More OCTEONIII support</title>
<updated>2015-02-20T14:32:46+00:00</updated>
<author>
<name>Chandrakala Chavva</name>
<email>cchavva@caviumnetworks.com</email>
</author>
<published>2015-01-15T13:11:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=ac6d9b3a03930820bec0ebd3a28f9dae32d27342'/>
<id>urn:sha1:ac6d9b3a03930820bec0ebd3a28f9dae32d27342</id>
<content type='text'>
Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII.

Signed-off-by: Chandrakala Chavva &lt;cchavva@caviumnetworks.com&gt;
Signed-off-by: Aleksey Makarov &lt;aleksey.makarov@auriga.com&gt;
Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8945/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.</title>
<updated>2015-02-20T14:31:59+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2015-01-15T13:11:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=726da2f82a1659da5d4d3473427fdb198ffde370'/>
<id>urn:sha1:726da2f82a1659da5d4d3473427fdb198ffde370</id>
<content type='text'>
Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Signed-off-by: Aleksey Makarov &lt;aleksey.makarov@auriga.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8943/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: OCTEON: Update octeon-model.h code for new SoCs.</title>
<updated>2015-02-20T14:31:43+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2015-01-15T13:11:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=debe6a623d3cdc7f0374124830587fb8d1a04b63'/>
<id>urn:sha1:debe6a623d3cdc7f0374124830587fb8d1a04b63</id>
<content type='text'>
Add coverage for OCTEON III models.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Signed-off-by: Aleksey Makarov &lt;aleksey.makarov@auriga.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8942/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX</title>
<updated>2015-02-20T14:31:27+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2015-01-15T13:11:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=e3d0ead59f6c1167c817ea338dd9395d517940e1'/>
<id>urn:sha1:e3d0ead59f6c1167c817ea338dd9395d517940e1</id>
<content type='text'>
Make messages refer to all CN6XXX.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Signed-off-by: Aleksey Makarov &lt;aleksey.makarov@auriga.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8941/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs</title>
<updated>2015-02-20T14:28:29+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2015-01-15T13:11:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=ac655fb7626ea63b12ee5f449a082c79db6d2f26'/>
<id>urn:sha1:ac655fb7626ea63b12ee5f449a082c79db6d2f26</id>
<content type='text'>
The wide multiplier is twice as wide, so we need to save twice as much
state.  Detect the multiplier type (CPU type) at start up and install
model specific handlers.

[aleksey.makarov@auriga.com:
	conflict resolution,
	support for old compilers]

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Signed-off-by: Leonid Rosenboim &lt;lrosenboim@caviumnetworks.com&gt;
Signed-off-by: Aleksey Makarov &lt;aleksey.makarov@auriga.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8933/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>treewide: fix typo in printk and Kconfig</title>
<updated>2014-11-20T13:56:11+00:00</updated>
<author>
<name>Masanari Iida</name>
<email>standby24x7@gmail.com</email>
</author>
<published>2014-11-05T13:26:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=6774def6422f6eac53f1828c317bf3b08a8f5a60'/>
<id>urn:sha1:6774def6422f6eac53f1828c317bf3b08a8f5a60</id>
<content type='text'>
This patch fix spelling typo in printk and Kconfig within
various part of kernel sources.

Signed-off-by: Masanari Iida &lt;standby24x7@gmail.com&gt;
Acked-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Signed-off-by: Jiri Kosina &lt;jkosina@suse.cz&gt;
</content>
</entry>
<entry>
<title>MIPS: Octeon: Remove special case for simulator command line.</title>
<updated>2014-10-22T17:37:03+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2014-10-20T22:44:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=b61cd31ee6cbe65f67a6ccba2bcbd3c702f52778'/>
<id>urn:sha1:b61cd31ee6cbe65f67a6ccba2bcbd3c702f52778</id>
<content type='text'>
There is no reason to have the kernel to append commands when running
under the simulator, the simulator is perfectly capable of supplying
the necessary command line arguments.  Furthermore, if the simulator
needs something different than what is hard coded in the kernel, it
cannot get it if the kernel overrides it.

Fix/Simplify the whole thing by removing this bit.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8152/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
</feed>
