<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/mips/ath79, branch dev-4.3</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.3</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.3'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2015-12-09T19:34:14+00:00</updated>
<entry>
<title>MIPS: ath79: Fix the DDR control initialization on ar71xx and ar934x</title>
<updated>2015-12-09T19:34:14+00:00</updated>
<author>
<name>Alban Bedel</name>
<email>albeu@free.fr</email>
</author>
<published>2015-11-17T08:40:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=e3301b7ef826632aa792add0f6d97ed577bc2ea9'/>
<id>urn:sha1:e3301b7ef826632aa792add0f6d97ed577bc2ea9</id>
<content type='text'>
commit 5011a7e808c9fec643d752c5a495a48f27268a48 upstream.

The DDR control initialization needs to know the SoC type, however
ath79_detect_sys_type() was called after ath79_ddr_ctrl_init().
Reverse the order to fix the DDR control initialization on ar71xx and
ar934x.

Signed-off-by: Alban Bedel &lt;albeu@free.fr&gt;
Cc: Felix Fietkau &lt;nbd@openwrt.org&gt;
Cc: Qais Yousef &lt;qais.yousef@imgtec.com&gt;
Cc: Andrew Bresticker &lt;abrestic@chromium.org&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11500/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>MIPS: ATH79: Add irq chip ar7240-misc-intc</title>
<updated>2015-09-22T17:07:11+00:00</updated>
<author>
<name>Alexander Couzens</name>
<email>lynxis@fe80.eu</email>
</author>
<published>2015-09-19T04:26:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=19446da415e0f01d56364b700fe984cda78bca50'/>
<id>urn:sha1:19446da415e0f01d56364b700fe984cda78bca50</id>
<content type='text'>
The ar7240 misc irq chip use ack handler
instead of ack_mask handler. All new ath79 chips use
the ar7240 misc irq chip

Signed-off-by: Alexander Couzens &lt;lynxis@fe80.eu&gt;
Acked-by: Alban Bedel &lt;albeu@free.fr&gt;
Acked-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: linux-mips@linux-mips.org
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: Pawel Moll &lt;pawel.moll@arm.com&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Ian Campbell &lt;ijc+devicetree@hellion.org.uk&gt;
Cc: Kumar Gala &lt;galak@codeaurora.org&gt;
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper &lt;jason@lakedaemon.net&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11164/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: ATH79: Set missing irq ack handler for ar7100-misc-intc irq chip</title>
<updated>2015-09-22T17:05:56+00:00</updated>
<author>
<name>Alexander Couzens</name>
<email>lynxis@fe80.eu</email>
</author>
<published>2015-09-19T04:26:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=84dedd71cf3bc61cc65ca43a48f7252344a1bb68'/>
<id>urn:sha1:84dedd71cf3bc61cc65ca43a48f7252344a1bb68</id>
<content type='text'>
The irq ack handler was forgotten while introducing OF support.
Only ar71xx and ar933x based devices require it.

Signed-off-by: Alexander Couzens &lt;lynxis@fe80.eu&gt;
Acked-by: Alban Bedel &lt;albeu@free.fr&gt;
Acked-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: linux-mips@linux-mips.org
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: Pawel Moll &lt;pawel.moll@arm.com&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Ian Campbell &lt;ijc+devicetree@hellion.org.uk&gt;
Cc: Kumar Gala &lt;galak@codeaurora.org&gt;
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper &lt;jason@lakedaemon.net&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11163/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>genirq: Remove irq argument from irq flow handlers</title>
<updated>2015-09-16T13:47:51+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2015-09-14T08:42:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=bd0b9ac405e1794d72533c3d487aa65b6b955a0c'/>
<id>urn:sha1:bd0b9ac405e1794d72533c3d487aa65b6b955a0c</id>
<content type='text'>
Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.

Remove the argument.

Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Julia Lawall &lt;Julia.Lawall@lip6.fr&gt;
Cc: Jiang Liu &lt;jiang.liu@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>MIPS: ath79: Move the GPIO driver to drivers/gpio</title>
<updated>2015-09-03T10:08:02+00:00</updated>
<author>
<name>Alban Bedel</name>
<email>albeu@free.fr</email>
</author>
<published>2015-07-03T09:11:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=1d473c2cb9fe25fc6bad30b0eb8d92e384496042'/>
<id>urn:sha1:1d473c2cb9fe25fc6bad30b0eb8d92e384496042</id>
<content type='text'>
GPIO drivers should be in drivers/gpio

Signed-off-by: Alban Bedel &lt;albeu@free.fr&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Cc: linux-gpio@vger.kernel.org
Cc: Alexandre Courbot &lt;gnurou@gmail.com&gt;
Cc: Gabor Juhos &lt;juhosg@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10597/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Ath79: Remove the unused GPIO function API</title>
<updated>2015-09-03T10:08:02+00:00</updated>
<author>
<name>Alban Bedel</name>
<email>albeu@free.fr</email>
</author>
<published>2015-07-03T09:11:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f689332b19fa1120de1bd84988a7bd0c08bd9b7b'/>
<id>urn:sha1:f689332b19fa1120de1bd84988a7bd0c08bd9b7b</id>
<content type='text'>
To prepare moving the GPIO driver to drivers/gpio remove the
platform specific pinmux API. As it is not used by any board,
and such functionality should better be implemented using the
pinmux subsystem just removing it seems to be the best option.

Signed-off-by: Alban Bedel &lt;albeu@free.fr&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Cc: linux-gpio@vger.kernel.org
Cc: Alexandre Courbot &lt;gnurou@gmail.com&gt;
Cc: Gabor Juhos &lt;juhosg@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10596/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: ath91: Remove pointless irqdisable/enable</title>
<updated>2015-08-26T13:23:31+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2015-07-13T20:46:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=9d9a2fa7dcbd05a1608a6a38b6ec1a092e117c3c'/>
<id>urn:sha1:9d9a2fa7dcbd05a1608a6a38b6ec1a092e117c3c</id>
<content type='text'>
The various interrupt flow handlers in ath79 are cascading interrupt
handlers. They all have a disable_irq_nosync()/enable_irq() pair
around the generic_handle_irq() call. The value of this disable/enable
is zero because its a complete noop:

disable_irq_nosync() merily increments the disable count without
actually masking the interrupt. enable_irq() soleley decrements the
disable count without touching the interrupt chip. The interrupt
cannot arrive again because the complete call chain runs with
interrupts disabled.

Remove it.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: linux-mips@linux-mips.org
Cc: LKML &lt;linux-kernel@vger.kernel.org&gt;
Cc: Jiang Liu &lt;jiang.liu@linux.intel.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/10703/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: ath79: irq: IRQCHIP_DECLARE moved to linux/irqchip.h</title>
<updated>2015-08-26T13:23:02+00:00</updated>
<author>
<name>Alban Bedel</name>
<email>albeu@free.fr</email>
</author>
<published>2015-07-09T08:51:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=7653716bf989cf8be04c7bedcad6bb201b1df108'/>
<id>urn:sha1:7653716bf989cf8be04c7bedcad6bb201b1df108</id>
<content type='text'>
Remove the ugly cross tree include now that IRQCHIP_DECLARE moved to
linux/irqchip.h.

Signed-off-by: Alban Bedel &lt;albeu@free.fr&gt;
Cc: linux-mips@linux-mips.org
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Andrew Bresticker &lt;abrestic@chromium.org&gt;
Cc: Qais Yousef &lt;qais.yousef@imgtec.com&gt;
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10633/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Export get_c0_perfcount_int()</title>
<updated>2015-08-03T07:25:18+00:00</updated>
<author>
<name>Felix Fietkau</name>
<email>nbd@openwrt.org</email>
</author>
<published>2015-07-23T16:59:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=0cb0985f57783c2f3c6c8ffe7e7665e80c56bd92'/>
<id>urn:sha1:0cb0985f57783c2f3c6c8ffe7e7665e80c56bd92</id>
<content type='text'>
get_c0_perfcount_int is tested from oprofile code. If oprofile is
compiled as module, get_c0_perfcount_int needs to be exported, otherwise
it cannot be resolved.

Fixes: a669efc4a3b4 ("MIPS: Add hook to get C0 performance counter interrupt")
Cc: stable@vger.kernel.org # v3.19+
Signed-off-by: Felix Fietkau &lt;nbd@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Cc: abrestic@chromium.org
Patchwork: https://patchwork.linux-mips.org/patch/10763/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Add basic support for the TL-WR1043ND version 1</title>
<updated>2015-06-21T19:54:10+00:00</updated>
<author>
<name>Alban Bedel</name>
<email>albeu@free.fr</email>
</author>
<published>2015-05-31T00:18:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=a5fcc6522fd43acba09aa9ffca09872aaf02cd5e'/>
<id>urn:sha1:a5fcc6522fd43acba09aa9ffca09872aaf02cd5e</id>
<content type='text'>
Add a DTS for TL-WR1043ND version 1 and allow to have it built in the
kernel to circumvent the broken u-boot found on these boards.
Currently only the UART, LEDs and buttons are supported.

Signed-off-by: Alban Bedel &lt;albeu@free.fr&gt;
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
</feed>
