BMC/Intel-BMC/linux.git/arch/mips/alchemy/common/time.c, branch dev

MIPS: Alchemy: introduce helpers to access SYS register block.

2014-07-30T11:53:28+00:00

This patch changes all absolute SYS_XY registers to offsets from the SYS block base, prefixes them with AU1000 to avoid silent failures due to changed addresses, and introduces helper functions to read/write them. No functional changes, comparing assembly of a few select functions shows no differences. Signed-off-by: Manuel Lauss Cc: Linux-MIPS Patchwork: https://patchwork.linux-mips.org/patch/7464/ Signed-off-by: Ralf Baechle

MIPS: Idle: Consolidate all declarations in .

2013-05-21T23:34:27+00:00

Signed-off-by: Ralf Baechle

MIPS: Whitespace cleanup.

2013-02-01T09:00:22+00:00

Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle

MIPS: Alchemy: Make 32kHz and r4k timer coexist peacefully

2012-12-27T15:27:35+00:00

Now that the r4k timer is registered no matter what, bump the rating of the Alchemy 32kHz timer so that it gets used when it is working, and fall back on the r4k when it isn't. This fixes a timer-related hang on platform with a working 32kHz timer (the better rated c0 timer stops while executing 'wait' leading to (almost) eternal sleep) and an oops on boot on platforms without a working 32kHz timer (due to double registration of the r4k timer). Signed-off-by: Manuel Lauss Cc: Linux-MIPS Patchwork: https://patchwork.linux-mips.org/patch/4728/ Signed-off-by: Ralf Baechle

MIPS: Alchemy: Increase minimum timeout for 32kHz timer.

2012-02-20T17:33:18+00:00

Since a clocksource change post 3.2-rc1, tasks on my DB1500 board hang after random amounts of time (from a few minutes to a few hours), regardless of load. Debugging showed that the compare-match register value is a few seconds lower than the current counter value. The minimum value of 8 was initialy determined by a trial-and-error approach. Currently it is sufficient for all Alchemys (without PCI apparently), independent of CPU clock; only the DB1500 and DB1550 boards experience these timer-related tasks hangs now. This patch increases the minimum timeout by 1 (to 9 counter ticks) which seems sufficient since the systems are still working perfectly fine after over 24 hours. Signed-off-by: Manuel Lauss Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3214/ Signed-off-by: Ralf Baechle

Merge branch 'next/alchemy' into mips-for-linux-next

2012-01-11T14:42:10+00:00

MIPS: irq: Remove IRQF_DISABLED

2011-12-07T22:03:45+00:00

Since commit [e58aa3d2: genirq: Run irq handlers with interrupts disabled], We run all interrupt handlers with interrupts disabled and we even check and yell when an interrupt handler returns with interrupts enabled (see commit [b738a50a: genirq: Warn when handler enables interrupts]). So now this flag is a NOOP and can be removed. [ralf@linux-mips.org: Fixed up conflicts in arch/mips/alchemy/common/dbdma.c, arch/mips/cavium-octeon/smp.c and arch/mips/kernel/perf_event.c.] Signed-off-by: Yong Zhang To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2835/ Signed-off-by: Ralf Baechle

MIPS: Alchemy: Au1300 SoC support

2011-12-07T22:02:05+00:00

Add basic support for the Au1300 variant(s): - New GPIO/Interrupt controller - DBDMA ids - USB setup - MMC support - enable various PSC drivers - detection code. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2866/ Signed-off-by: Ralf Baechle

mips: convert to clocksource_register_hz/khz

2011-02-21T21:33:50+00:00

This converts the mips clocksources to use clocksource_register_hz/khz CC: Ralf Baechle CC: Thomas Gleixner Signed-off-by: John Stultz

MIPS: Alchemy: Stop IRQ name sharing

2010-02-27T11:52:53+00:00

Eliminate the sharing of IRQ names among the differenct Alchemy variants. IRQ numbers need no longer be hidden behind a CONFIG_SOC_AU1XXX symbol: step 1 in my quest to make the Alchemy code less reliant on a hardcoded subtype. This patch also renames the GPIO irq number constants. It's really an interrupt line, NOT a GPIO number! Code which relied on certain irq numbers to have the same name across all supported cpu subtypes is changed to determine current cpu subtype at runtime; in some places this isn't possible so a "compat" symbol is used. Run-tested on DB1200. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle