<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/mips/alchemy/common/Makefile, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2014-07-30T12:12:00+00:00</updated>
<entry>
<title>MIPS: Alchemy: remove old clock support</title>
<updated>2014-07-30T12:12:00+00:00</updated>
<author>
<name>Manuel Lauss</name>
<email>manuel.lauss@gmail.com</email>
</author>
<published>2014-07-23T14:36:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=72e1e2a30f67fc19a958be6c1818e7e6cb1573fe'/>
<id>urn:sha1:72e1e2a30f67fc19a958be6c1818e7e6cb1573fe</id>
<content type='text'>
With the clock framework in place, remove unused functions and bits,
and drop the CLK_IGNORE_UNUSED flag, which is now unneeded.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@gmail.com&gt;
Cc: Linux-MIPS &lt;linux-mips@linux-mips.org&gt;
Patchwork: https://patchwork.linux-mips.org/patch/7473/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Alchemy: clock framework integration of onchip clocks</title>
<updated>2014-07-30T12:08:42+00:00</updated>
<author>
<name>Manuel Lauss</name>
<email>manuel.lauss@gmail.com</email>
</author>
<published>2014-07-23T14:36:48+00:00</published>
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<id>urn:sha1:474402291a0ad4778a4e5fdff6ae507b2a26d809</id>
<content type='text'>
This patch introduces common clock framework integration for all
configurable on-chip clocks on Alchemy chips:

- 2 or 3 PLLs which generate integer multiples of the root rate 12MHz,
- 6 dividers which take one of the 3 PLLs as input and divide their
  rate by either multiples of 2 or 1 (Au1300).
- another bank of up to 6 muxes which take either one of the 6
  above dividers or one of the PLLs directly and divide their rate
  further by 1, 2, 3 or 4.
- a few other sources which are used by onchip peripherals and are
  informational.

This implementation will take the clock tree as it was set up
by boot firmware: all in-kernel boards should continue to work
without having to set up the clock tree in board code.

CLK_IGNORE_DISABLED will be removed once all drivers have been
converted.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@gmail.com&gt;
Cc: Mike Turquette &lt;mturquette@linaro.org&gt;
Cc: Linux-MIPS &lt;linux-mips@linux-mips.org&gt;
Patchwork: https://patchwork.linux-mips.org/patch/7466/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>USB: move common alchemy USB routines to arch/mips/alchemy/common.c</title>
<updated>2012-10-22T18:29:12+00:00</updated>
<author>
<name>Florian Fainelli</name>
<email>florian@openwrt.org</email>
</author>
<published>2012-10-08T13:11:40+00:00</published>
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<id>urn:sha1:216d0fded417d26a19049038788813af126b9d66</id>
<content type='text'>
A previous patch converted the Alchemy platform to use the OHCI and EHCI
platform drivers. As a result, all the common logic to handle USB present in
drivers/usb/host/alchemy-common.c has no reason to remain here, so we move it
to arch/mips/alchemy/common/usb.c which is a more appropriate place. This
change was suggested by Manuel Lauss.

Signed-off-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Acked-by: Alan Stern &lt;stern@rowland.harvard.edu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Alchemy: merge Au1000 and Au1300-style IRQ controller code.</title>
<updated>2011-12-08T10:42:16+00:00</updated>
<author>
<name>Manuel Lauss</name>
<email>manuel.lauss@googlemail.com</email>
</author>
<published>2011-12-08T10:42:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=3eab8095ef1658f5cd4927a0224b1214329cb348'/>
<id>urn:sha1:3eab8095ef1658f5cd4927a0224b1214329cb348</id>
<content type='text'>
With a generic plat_irq_dispatch (for Alchemy at least) code for both
interrupt controller types can coexist in a single kernel image and be
autodetected at runtime.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@googlemail.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2935/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Alchemy: Au1300 SoC support</title>
<updated>2011-12-07T22:02:05+00:00</updated>
<author>
<name>Manuel Lauss</name>
<email>manuel.lauss@googlemail.com</email>
</author>
<published>2011-11-01T19:03:30+00:00</published>
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<id>urn:sha1:809f36c6f4a0568178c909ff1096ca83eae33f7d</id>
<content type='text'>
Add basic support for the Au1300 variant(s):
- New GPIO/Interrupt controller
- DBDMA ids
- USB setup
- MMC support
- enable various PSC drivers
- detection code.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@googlemail.com&gt;
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2866/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Alchemy: Redo PCI as platform driver</title>
<updated>2011-10-24T22:34:24+00:00</updated>
<author>
<name>Manuel Lauss</name>
<email>manuel.lauss@googlemail.com</email>
</author>
<published>2011-08-12T09:39:44+00:00</published>
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<id>urn:sha1:7517de348663b08a808aff44b5300e817157a568</id>
<content type='text'>
- Rewrite Alchemy PCI support as a platform driver.
- Fixup boards which have PCI.

Run-tested on DB1500 and DB1550.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@googlemail.com&gt;
To: Linux-MIPS &lt;linux-mips@linux-mips.org&gt;
Patchwork: https://patchwork.linux-mips.org/patch/2706/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;

 delete mode 100644 arch/mips/alchemy/common/pci.c
 delete mode 100644 arch/mips/pci/fixup-au1000.c
 delete mode 100644 arch/mips/pci/ops-au1000.c
 create mode 100644 arch/mips/pci/pci-alchemy.c
</content>
</entry>
<entry>
<title>MIPS: Alchemy: support multiple GPIO styles in one kernel</title>
<updated>2011-10-24T22:34:23+00:00</updated>
<author>
<name>Manuel Lauss</name>
<email>manuel.lauss@googlemail.com</email>
</author>
<published>2011-08-02T17:51:03+00:00</published>
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<id>urn:sha1:ce1d43b9a9e8a3db8fe91696c0b0e3ac1a154e34</id>
<content type='text'>
For GPIOLIB=y decide at runtime which gpiochips to register;
in the GPIOLIB=n case, the gpio headers need to be reshuffled
a bit to make multiple implementations coexist peacefully.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@googlemail.com&gt;
To: Linux-MIPS &lt;linux-mips@linux-mips.org&gt;
Patchwork: https://patchwork.linux-mips.org/patch/2679/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Move Alchemy Makefile parts to their own Platform file.</title>
<updated>2010-08-05T12:25:46+00:00</updated>
<author>
<name>Manuel Lauss</name>
<email>manuel.lauss@googlemail.com</email>
</author>
<published>2010-06-01T20:30:37+00:00</published>
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<id>urn:sha1:baf3eb233df301081b66637a257ce0e9f6f84706</id>
<content type='text'>
[Ralf: Remove a forgotten -Werror in Pb1200 Makefile.]

Signed-off-by: Manuel Lauss &lt;manuel.lauss@googlemail.com&gt;
To: Linux-MIPS &lt;linux-mips@linux-mips.org&gt;
Cc: Sam Ravnborg &lt;sam@ravnborg.org&gt;
Cc: Manuel Lauss &lt;manuel.lauss@googlemail.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/1319/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Alchemy: get rid of common/reset.c</title>
<updated>2010-02-27T11:53:04+00:00</updated>
<author>
<name>Manuel Lauss</name>
<email>manuel.lauss@googlemail.com</email>
</author>
<published>2009-12-08T18:18:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=32fd6901a6d8d19f94e4de6be4e4b552ab078620'/>
<id>urn:sha1:32fd6901a6d8d19f94e4de6be4e4b552ab078620</id>
<content type='text'>
Implement reset / poweroff in the board code instead.  The peripheral reset
code is gone too since YAMON which all in-tree boards use does the same
work when it boots.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@gmail.com&gt;
Signed-off-by: Yoichi Yuasa &lt;yuasa@linux-mips.org&gt;
Cc: Linux-MIPS &lt;linux-mips@linux-mips.org&gt;
Patchwork: http://patchwork.linux-mips.org/patch/783/
Patchwork: http://patchwork.linux-mips.org/patch/882/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Alchemy: Only build AU1000 INTC code for compatible cpus</title>
<updated>2010-02-27T11:53:02+00:00</updated>
<author>
<name>Manuel Lauss</name>
<email>manuel.lauss@googlemail.com</email>
</author>
<published>2009-11-23T19:40:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=5d400f5c59df3ed2c3682a7409c8e81a7c4e650c'/>
<id>urn:sha1:5d400f5c59df3ed2c3682a7409c8e81a7c4e650c</id>
<content type='text'>
Use the GPIO config symbol to only build Au1000 interrupt code on chips with
compatible hw.

Signed-off-by: Manuel Lauss &lt;manuel.lauss@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/670/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
</feed>
