<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/mips/Kconfig, branch dev-5.7</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.7</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.7'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2020-04-04T17:12:47+00:00</updated>
<entry>
<title>Merge tag 'dma-mapping-5.7' of git://git.infradead.org/users/hch/dma-mapping</title>
<updated>2020-04-04T17:12:47+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-04-04T17:12:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=6f43bae38269a55534e1f86a9917318167de6639'/>
<id>urn:sha1:6f43bae38269a55534e1f86a9917318167de6639</id>
<content type='text'>
Pull dma-mapping updates from Christoph Hellwig:

 - fix an integer overflow in the coherent pool (Kevin Grandemange)

 - provide support for in-place uncached remapping and use that for
   openrisc

 - fix the arm coherent allocator to take the bus limit into account

* tag 'dma-mapping-5.7' of git://git.infradead.org/users/hch/dma-mapping:
  ARM/dma-mapping: merge __dma_supported into arm_dma_supported
  ARM/dma-mapping: take the bus limit into account in __dma_alloc
  ARM/dma-mapping: remove get_coherent_dma_mask
  openrisc: use the generic in-place uncached DMA allocator
  dma-direct: provide a arch_dma_clear_uncached hook
  dma-direct: make uncached_kernel_address more general
  dma-direct: consolidate the error handling in dma_direct_alloc_pages
  dma-direct: remove the cached_kernel_address hook
  dma-coherent: fix integer overflow in the reserved-memory dma allocation
</content>
</entry>
<entry>
<title>Merge tag 'mips_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux</title>
<updated>2020-03-31T15:51:45+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-03-31T15:51:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=d71e064449a704a026fa032ec852d532f08aefa1'/>
<id>urn:sha1:d71e064449a704a026fa032ec852d532f08aefa1</id>
<content type='text'>
Pull MIPS updates from Thomas Bogendoerfer:

 - loongson64 irq rework

 - dmi support loongson

 - replace setup_irq() by request_irq()

 - jazz cleanups

 - minor cleanups and fixes

* tag 'mips_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (44 commits)
  MIPS: ralink: mt7621: Fix soc_device introduction
  MIPS: Exclude more dsemul code when CONFIG_MIPS_FP_SUPPORT=n
  MIPS/tlbex: Fix LDDIR usage in setup_pw() for Loongson-3
  MIPS: do not compile generic functions for CONFIG_CAVIUM_OCTEON_SOC
  MAINTAINERS: Update Loongson64 entry
  MIPS: Loongson64: Load built-in dtbs
  MIPS: Loongson64: Add generic dts
  dt-bindings: mips: Add loongson boards
  MIPS: Loongson64: Drop legacy IRQ code
  dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
  irqchip: Add driver for Loongson-3 HyperTransport PIC controller
  dt-bindings: interrupt-controller: Add Loongson LIOINTC
  irqchip: loongson-liointc: Workaround LPC IRQ Errata
  irqchip: Add driver for Loongson I/O Local Interrupt Controller
  docs: mips: remove no longer needed au1xxx_ide.rst documentation
  MIPS: Alchemy: remove no longer used au1xxx_ide.h header
  ide: remove no longer used au1xxx-ide driver
  MIPS: Add support for Desktop Management Interface (DMI)
  firmware: dmi: Add macro SMBIOS_ENTRY_POINT_SCAN_START
  MIPS: ralink: mt7621: introduce 'soc_device' initialization
  ...
</content>
</entry>
<entry>
<title>Merge tag 'timers-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2020-03-31T01:51:47+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-03-31T01:51:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=dbb381b619aa5242c9cb1a8fd54d71c4d79c91eb'/>
<id>urn:sha1:dbb381b619aa5242c9cb1a8fd54d71c4d79c91eb</id>
<content type='text'>
Pull timekeeping and timer updates from Thomas Gleixner:
 "Core:

   - Consolidation of the vDSO build infrastructure to address the
     difficulties of cross-builds for ARM64 compat vDSO libraries by
     restricting the exposure of header content to the vDSO build.

     This is achieved by splitting out header content into separate
     headers. which contain only the minimaly required information which
     is necessary to build the vDSO. These new headers are included from
     the kernel headers and the vDSO specific files.

   - Enhancements to the generic vDSO library allowing more fine grained
     control over the compiled in code, further reducing architecture
     specific storage and preparing for adopting the generic library by
     PPC.

   - Cleanup and consolidation of the exit related code in posix CPU
     timers.

   - Small cleanups and enhancements here and there

  Drivers:

   - The obligatory new drivers: Ingenic JZ47xx and X1000 TCU support

   - Correct the clock rate of PIT64b global clock

   - setup_irq() cleanup

   - Preparation for PWM and suspend support for the TI DM timer

   - Expand the fttmr010 driver to support ast2600 systems

   - The usual small fixes, enhancements and cleanups all over the
     place"

* tag 'timers-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (80 commits)
  Revert "clocksource/drivers/timer-probe: Avoid creating dead devices"
  vdso: Fix clocksource.h macro detection
  um: Fix header inclusion
  arm64: vdso32: Enable Clang Compilation
  lib/vdso: Enable common headers
  arm: vdso: Enable arm to use common headers
  x86/vdso: Enable x86 to use common headers
  mips: vdso: Enable mips to use common headers
  arm64: vdso32: Include common headers in the vdso library
  arm64: vdso: Include common headers in the vdso library
  arm64: Introduce asm/vdso/processor.h
  arm64: vdso32: Code clean up
  linux/elfnote.h: Replace elf.h with UAPI equivalent
  scripts: Fix the inclusion order in modpost
  common: Introduce processor.h
  linux/ktime.h: Extract common header for vDSO
  linux/jiffies.h: Extract common header for vDSO
  linux/time64.h: Extract common header for vDSO
  linux/time32.h: Extract common header for vDSO
  linux/time.h: Extract common header for vDSO
  ...
</content>
</entry>
<entry>
<title>MIPS: do not compile generic functions for CONFIG_CAVIUM_OCTEON_SOC</title>
<updated>2020-03-25T15:07:13+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>masahiroy@kernel.org</email>
</author>
<published>2020-03-25T07:45:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=78bdbbac08d7383b5c8a2b489ae789049704b046'/>
<id>urn:sha1:78bdbbac08d7383b5c8a2b489ae789049704b046</id>
<content type='text'>
MIPS provides multiple definitions for the following functions:

  fw_init_cmdline
  __delay
  __udelay
  __ndelay
  memmove
  __rmemcpy
  memcpy
  __copy_user

The generic ones are defined in lib-y objects, which are overridden by
the Octeon ones when CONFIG_CAVIUM_OCTEON_SOC is enabled.

The use of EXPORT_SYMBOL in static libraries potentially causes a
problem for the llvm linker [1]. So, I want to forcibly link lib-y
objects to vmlinux when CONFIG_MODULES=y.

As a groundwork, we must fix multiple definitions that have previously
been hidden by lib-y.

If you look at lib/string.c, arch can define __HAVE_ARCH_* to opt out
the generic implementation.

Similarly, this commit adds CONFIG_HAVE_PLAT_* to allow a platform
to opt out the MIPS generic code.

[1]: https://github.com/ClangBuiltLinux/linux/issues/515

Reported-by: kbuild test robot &lt;lkp@intel.com&gt;
Signed-off-by: Masahiro Yamada &lt;masahiroy@kernel.org&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Loongson64: Add generic dts</title>
<updated>2020-03-25T15:07:12+00:00</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2020-03-25T03:55:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=87fcfa7b7fe6bf819033fe827a27f710e38639b5'/>
<id>urn:sha1:87fcfa7b7fe6bf819033fe827a27f710e38639b5</id>
<content type='text'>
Add generic device dts for Loongson-3 devices.
They are currently almost identical but will be different later.
Some PCH devices like PCI Host Bridge is still enabled by platform
code for now.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Co-developed-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Add support for Desktop Management Interface (DMI)</title>
<updated>2020-03-23T14:44:05+00:00</updated>
<author>
<name>Tiezhu Yang</name>
<email>yangtiezhu@loongson.cn</email>
</author>
<published>2020-02-05T04:08:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=be8fa1cb444cdf3dcab72053939d073394886ff8'/>
<id>urn:sha1:be8fa1cb444cdf3dcab72053939d073394886ff8</id>
<content type='text'>
Enable DMI scanning on the MIPS architecture, this setups DMI identifiers
(dmi_system_id) for printing it out on task dumps and prepares DIMM entry
information (dmi_memdev_info) from the SMBIOS table. With this patch, the
driver can easily match various of mainboards.

In the SMBIOS reference specification, the table anchor string "_SM_" is
present in the address range 0xF0000 to 0xFFFFF on a 16-byte boundary,
but there exists a special case for Loongson platform, when call function
dmi_early_remap, it should specify the start address to 0xFFFE000 due to
it is reserved for SMBIOS and can be normally access in the BIOS.

This patch works fine on the Loongson 3A3000 platform which belongs to
MIPS architecture and has no influence on the other architectures such
as x86 and ARM.

Additionally, in order to avoid the unknown risks on the mips platform
which is not MACH_LOONGSON64, the DMI config is better to depend on
MACH_LOONGSON64. If other mips platform also needs this DMI feature in
the future, the "depends on" condition can be modified.

Co-developed-by: Yinglu Yang &lt;yangyinglu@loongson.cn&gt;
Signed-off-by: Yinglu Yang &lt;yangyinglu@loongson.cn&gt;
[jiaxun.yang@flygoat.com: Refine definitions and Kconfig]
Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Tiezhu Yang &lt;yangtiezhu@loongson.cn&gt;
Reviewed-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>dma-direct: make uncached_kernel_address more general</title>
<updated>2020-03-16T09:48:09+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2020-02-21T23:55:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=fa7e2247c5729f990c7456fe09f3af99c8f2571b'/>
<id>urn:sha1:fa7e2247c5729f990c7456fe09f3af99c8f2571b</id>
<content type='text'>
Rename the symbol to arch_dma_set_uncached, and pass a size to it as
well as allow an error return.  That will allow reusing this hook for
in-place pagetable remapping.

As the in-place remap doesn't always require an explicit cache flush,
also detangle ARCH_HAS_DMA_PREP_COHERENT from ARCH_HAS_DMA_SET_UNCACHED.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
</content>
</entry>
<entry>
<title>arch/mips: change duplicated word in NUMA help text</title>
<updated>2020-03-04T20:18:00+00:00</updated>
<author>
<name>Randy Dunlap</name>
<email>rdunlap@infradead.org</email>
</author>
<published>2020-02-01T01:55:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=172a37e9d011510aee37f62cc5ac4e53e49d17bb'/>
<id>urn:sha1:172a37e9d011510aee37f62cc5ac4e53e49d17bb</id>
<content type='text'>
Fix wording in NUMA help text.

Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Paul Burton &lt;paulburton@kernel.org&gt;
Cc: linux-mips@vger.kernel.org
Reviewed-by: Philippe Mathieu-Daudé &lt;f4bug@amsat.org&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>lib/vdso: Cleanup clock mode storage leftovers</title>
<updated>2020-02-17T19:12:17+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2020-02-07T12:38:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f86fd32db706613fe8d0104057efa6e83e0d7e8f'/>
<id>urn:sha1:f86fd32db706613fe8d0104057efa6e83e0d7e8f</id>
<content type='text'>
Now that all architectures are converted to use the generic storage the
helpers and conditionals can be removed.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Vincenzo Frascino &lt;vincenzo.frascino@arm.com&gt;
Reviewed-by: Vincenzo Frascino &lt;vincenzo.frascino@arm.com&gt;
Link: https://lkml.kernel.org/r/20200207124403.470699892@linutronix.de



</content>
</entry>
<entry>
<title>mips: vdso: Use generic VDSO clock mode storage</title>
<updated>2020-02-17T19:12:16+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2020-02-07T12:38:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=e1bdb22ebe5363ed75ddedf836ca9f19e1195337'/>
<id>urn:sha1:e1bdb22ebe5363ed75ddedf836ca9f19e1195337</id>
<content type='text'>
Switch to the generic VDSO clock mode storage.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Vincenzo Frascino &lt;vincenzo.frascino@arm.com&gt;
Link: https://lkml.kernel.org/r/20200207124403.244684017@linutronix.de



</content>
</entry>
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