<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/m32r/include/asm/io.h, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
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<updated>2015-07-24T01:08:28+00:00</updated>
<entry>
<title>m32r: Add ioreadXX/iowriteXX big-endian mmio accessors</title>
<updated>2015-07-24T01:08:28+00:00</updated>
<author>
<name>Peter Hurley</name>
<email>peter@hurleysoftware.com</email>
</author>
<published>2015-07-09T03:10:06+00:00</published>
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<id>urn:sha1:7525a9901b5ee3c84933ad069e41506c37404ddc</id>
<content type='text'>
commit c627f2ceb692 ("serial: 8250: Add support for big-endian MMIO accesses")
added support for 32-bit big-endian mmio to the 8250 driver. Support for
ioreadXXbe/iowriteXXbe io accessors was missing from m32r arch, which caused
build errors.

Add trivial macro mmio accessors.

Reported-by: Fengguang Wu &lt;fengguang.wu@intel.com&gt;
Cc: Kevin Cernekee &lt;cernekee@gmail.com&gt;
Signed-off-by: Peter Hurley &lt;peter@hurleysoftware.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>arch/*/io.h: Add ioremap_wt() to all architectures</title>
<updated>2015-06-07T13:28:57+00:00</updated>
<author>
<name>Toshi Kani</name>
<email>toshi.kani@hp.com</email>
</author>
<published>2015-06-04T16:55:16+00:00</published>
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<id>urn:sha1:556269c138a8b2d3f5714b8105fa6119ecc505f2</id>
<content type='text'>
Add ioremap_wt() to all arch-specific asm/io.h headers which
define ioremap_wc() locally. These headers do not include
&lt;asm-generic/iomap.h&gt;. Some of them include &lt;asm-generic/io.h&gt;,
but ioremap_wt() is defined for consistency since they define
all ioremap_xxx locally.

In all architectures without Write-Through support, ioremap_wt()
is defined indentical to ioremap_nocache().

frv and m68k already have ioremap_writethrough(). On those we
add ioremap_wt() indetical to ioremap_writethrough() and defines
ARCH_HAS_IOREMAP_WT in both architectures.

The ioremap_wt() interface is exported to drivers.

Signed-off-by: Toshi Kani &lt;toshi.kani@hp.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Cc: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Cc: Andy Lutomirski &lt;luto@amacapital.net&gt;
Cc: Elliott@hp.com
Cc: H. Peter Anvin &lt;hpa@zytor.com&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Luis R. Rodriguez &lt;mcgrof@suse.com&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: arnd@arndb.de
Cc: hch@lst.de
Cc: hmh@hmh.eng.br
Cc: jgross@suse.com
Cc: konrad.wilk@oracle.com
Cc: linux-mm &lt;linux-mm@kvack.org&gt;
Cc: linux-nvdimm@lists.01.org
Cc: stefan.bader@canonical.com
Cc: yigal@plexistor.com
Link: http://lkml.kernel.org/r/1433436928-31903-9-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>m32r: add definition of ioremap_wc to io.h</title>
<updated>2015-03-16T20:11:32+00:00</updated>
<author>
<name>Abhilash Kesavan</name>
<email>a.kesavan@samsung.com</email>
</author>
<published>2015-02-06T13:45:26+00:00</published>
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<id>urn:sha1:71a49d16f06de2ccdf52ca247d496a2bb1ca36fe</id>
<content type='text'>
Before adding a resource managed ioremap_wc function, we need
to have ioremap_wc defined for m32r to prevent build errors.

Signed-off-by: Abhilash Kesavan &lt;a.kesavan@samsung.com&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>m32r: io: implement dummy relaxed accessor macros for writes</title>
<updated>2014-10-20T17:49:17+00:00</updated>
<author>
<name>Will Deacon</name>
<email>will.deacon@arm.com</email>
</author>
<published>2013-09-03T18:11:58+00:00</published>
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<id>urn:sha1:cb147c0f0b33f5ba37dfd07014f2973a53bc5d62</id>
<content type='text'>
write{b,w,l}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.

This patch adds dummy macros for the write accessors to m32r, in the
same vein as the dummy definitions for the relaxed read accessors.

Cc: Hirokazu Takata &lt;takata@linux-m32r.org&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>m32r: define ioread* and iowrite* macros</title>
<updated>2009-10-04T03:02:36+00:00</updated>
<author>
<name>Hirokazu Takata</name>
<email>takata@linux-m32r.org</email>
</author>
<published>2009-08-26T04:04:33+00:00</published>
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<id>urn:sha1:d2c5821c5de08175096f17166984d5e738cad024</id>
<content type='text'>
Define ioread* and iowrite* macros to fix the following build errors:

  CC [M]  drivers/uio/uio_smx.o
drivers/uio/uio_smx.c: In function 'smx_handler':
drivers/uio/uio_smx.c:31: error: implicit declaration of function 'ioread32'
drivers/uio/uio_smx.c:37: error: implicit declaration of function 'iowrite32'

Signed-off-by: Hirokazu Takata &lt;takata@linux-m32r.org&gt;
</content>
</entry>
<entry>
<title>m32r: move include/asm-m32r headers to arch/m32r/include/asm</title>
<updated>2009-04-17T01:05:01+00:00</updated>
<author>
<name>Hirokazu Takata</name>
<email>takata@linux-m32r.org</email>
</author>
<published>2008-11-27T17:46:48+00:00</published>
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<id>urn:sha1:fe4e719d82c4052751d2287de4bd18bd04e93685</id>
<content type='text'>
Signed-off-by: Hirokazu Takata &lt;takata@linux-m32r.org&gt;
</content>
</entry>
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