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<title>BMC/Intel-BMC/linux.git/arch/c6x/include/asm/irqflags.h, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
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<updated>2013-04-09T19:35:46+00:00</updated>
<entry>
<title>add memory barrier to arch_local_irq_restore</title>
<updated>2013-04-09T19:35:46+00:00</updated>
<author>
<name>Mark Salter</name>
<email>msalter@redhat.com</email>
</author>
<published>2013-04-09T19:35:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f934af05cb1bf20558542185299394a69060b829'/>
<id>urn:sha1:f934af05cb1bf20558542185299394a69060b829</id>
<content type='text'>
arch_local_irq_save() and friends are required to act as compiler
memory barriers. This patch adds a "memory" clobber to the inline
asm code in arch_local_irq_restore() which is used as the building
block for other functions needing to set/clear the interrupt enable
in the CSR register.

Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
</content>
</entry>
<entry>
<title>C6X: interrupt handling</title>
<updated>2011-10-06T23:47:54+00:00</updated>
<author>
<name>Aurelien Jacquiot</name>
<email>a-jacquiot@ti.com</email>
</author>
<published>2011-10-04T15:06:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=ec500af3059b474df35418c41c684c1cde830c81'/>
<id>urn:sha1:ec500af3059b474df35418c41c684c1cde830c81</id>
<content type='text'>
Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter &lt;msalter@redhat.com&gt;

Signed-off-by: Aurelien Jacquiot &lt;a-jacquiot@ti.com&gt;
Signed-off-by: Mark Salter &lt;msalter@redhat.com&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
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