BMC/Intel-BMC/linux.git/arch/blackfin/kernel/cplb-nompu, branch dev

bfin cache: dcplb map: add 16M dcplb map for BF60x

2013-05-09T10:22:45+00:00

use 16M data cplb map on BF60x to avoid too much dcplb miss overhead cleanup cplb info Signed-off-by: Steven Miao

blackfin: cplb-nompu: fix ROM cplb size for bf609-ezkit

2012-07-24T05:39:53+00:00

In user xip test, there is a cplb error when ROMKERNEL try to mount romfs using 'mount -t romfs /dev/mtdblock2 /mnt', becasue the CPLB setting is not correct. Signed-off-by: Bob Liu

blackfin: cplb: add support for bf60x

2012-05-21T06:54:16+00:00

Bf60x support big CPLB pages, this commit enable it. Signed-off-by: Bob Liu

Blackfin: no-mpu: fix masking of small uncached dma region

2011-01-10T12:18:18+00:00

When using an uncached DMA region less than 1 MiB, we try to mask off the whole last 1 MiB for it. Unfortunately, this fails as we forgot to subtract one from the calculated mask, leading to the region still be marked as cacheable. Reported-by: Andrew Rook Signed-off-by: Sonic Zhang Signed-off-by: Mike Frysinger

Blackfin: initial XIP support

2010-03-09T05:30:48+00:00

Signed-off-by: Barry Song Signed-off-by: Mike Frysinger

Blackfin: NOMPU: skip DMA ICPLB hole when it is redundant

2009-12-15T05:16:54+00:00

Normally there is no user-reserved memory after the DMA region which means there is no user-reserved ICPLB coverage. So the DMA hole can be covered by the large hole that is always added to cover up to the async bank. We only need an explicit DMA whole when we also add an explicit mapping for the user-reserved memory. Signed-off-by: Mike Frysinger

Blackfin: support smaller uncached DMA chunks for memory constrained systems

2009-12-15T05:15:48+00:00

When working with 8 meg systems, forcing a 1 meg DMA chunk heavily cuts into the available resources. So support smaller chunks to better cover needs for these systems. Signed-off-by: Barry Song Signed-off-by: Mike Frysinger

Blackfin: mass clean up of copyright/licensing info

2009-10-07T08:36:26+00:00

Bill Gatliff & David Brownell pointed out we were missing some copyrights, and licensing terms in some of the files in ./arch/blackfin, so this fixes things, and cleans them up. It also removes: - verbose GPL text(refer to the top level ./COPYING file) - file names (you are looking at the file) - bug url (it's in the ./MAINTAINERS file) - "or later" on GPL-2, when we did not have that right It also allows some Blackfin-specific assembly files to be under a BSD like license (for people to use them outside of Linux). Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger

Blackfin: unify cache init functions

2009-09-17T02:10:49+00:00

The CPLB implementations (mpu/nompu) had exact copies of the cacheinit code. Even the i/d cache functions are largely the same. So unify them both in the common kernel cache code. Signed-off-by: Mike Frysinger

Blackfin: add ICPLB coverage for async banks

2009-09-17T02:10:42+00:00

When doing XIP, we need to execute out of the async banks, so we need ICPLBs to allow this. Signed-off-by: Bernd Schmidt Signed-off-by: Mike Frysinger