BMC/Intel-BMC/linux.git/arch/arm, branch dev-5.2Intel OpenBMC Linux kernel source tree (mirror)https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-5.22019-09-10T23:18:23+00:00ARM: configs: aspeed-g5: Enable ext4 and dm2019-09-10T23:18:23+00:00Joel Stanleyjoel@jms.id.au2019-09-10T19:00:30+00:00urn:sha1:9f4f5ff36be2d4ec6694fae85ad0123da4674ba6
Signed-off-by: Joel Stanley <joel@jms.id.au>
ARM: dts: aspeed-g6: Add gpio devices2019-09-10T17:29:57+00:00Rashmica Guptarashmica.g@gmail.com2019-08-22T07:13:15+00:00urn:sha1:a25bc8d555c445b7e1acd8227aa832b19eedb914
The AST2600 has 208 normal GPIO pins and 36 1.8V GPIOs.
OpenBMC-Staging-Count: 1
Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
ARM: dts: aspeed-g5: Fix gpio-ranges upper limit2019-09-05T00:52:51+00:00Oscar A Perezlinux@neuralgames.com2019-05-01T13:26:43+00:00urn:sha1:bd0d4811c25d852f7c91ac0ce870494e17e10147
According to the AST2500/AST2520 specs, these SoCs support up to 228 GPIO
pins. However, 'gpio-ranges' value in 'aspeed-g5.dtsi' file is currently
setting the upper limit to 220 which isn't allowing access to all their
GPIOs. The correct upper limit value is 232 (actual number is 228 plus a
4-GPIO hole in GPIOAB). Without this patch, GPIOs AC5 and AC6 do not work
correctly on a AST2500 BMC running Linux Kernel v4.19
Fixes: 2039f90d136c ("ARM: dts: aspeed-g5: Add gpio controller to devicetree")
Signed-off-by: Oscar A Perez <linux@neuralgames.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
(cherry picked from commit 89b97c429e2e77d695b5133572ca12ec256a4ea4)
Signed-off-by: Joel Stanley <joel@jms.id.au>
ARM; dts: aspeed: mihawk: File should not be executable2019-09-05T00:52:43+00:00Joel Stanleyjoel@jms.id.au2019-09-04T17:18:36+00:00urn:sha1:c4c6206a5696a6ea7d1b55ccf14b916ad8f1b0a8
Remove the executable bit.
Fixes: 0a1dcf954ece ("ARM: dts: aspeed: Add Mihawk BMC platform")
Signed-off-by: Joel Stanley <joel@jms.id.au>
(cherry picked from commit db3a766d2eeeb4ff4a8ce3a55f0a21c65050dd06)
Signed-off-by: Joel Stanley <joel@jms.id.au>
ARM: dts: aspeed: swift: Change power supplies to version 22019-09-05T00:52:43+00:00Eddie Jameseajames@linux.ibm.com2019-08-30T19:11:02+00:00urn:sha1:9fe765b1845cf4eb247607714602bd661e575ce9
Swift power supplies are version 2 of the IBM CFFPS.
Fixes: 8e8fd0cbd7c5 ("ARM: dts: aspeed: Add Swift BMC machine")
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
(cherry picked from commit 020cdf3a51f666ccd980fe79a4586b22363d3984)
Signed-off-by: Joel Stanley <joel@jms.id.au>
ARM: dts: aspeed: vesnin: Add secondary SPI flash chip2019-09-05T00:52:43+00:00Ivan Mikhaylovi.mikhaylov@yadro.com2019-08-28T10:24:00+00:00urn:sha1:dfe51eb15b61aeaea69c42dc07a9773ba2e85267
Adds secondary SPI flash chip into dts for vesnin.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
(cherry picked from commit 659b7a4bd797597febd03c0fb7a286ee4da16732)
Signed-off-by: Joel Stanley <joel@jms.id.au>
ARM: dts: aspeed: vesnin: Add wdt2 with alt-boot option2019-09-05T00:52:43+00:00Ivan Mikhaylovi.mikhaylov@yadro.com2019-08-28T10:23:59+00:00urn:sha1:601ae250d40b81e4872aa7cc4eb66c46058be07c
Adds wdt2 section with 'alt-boot' option into dts for vesnin.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
(cherry picked from commit 9d463f8a180bbee1bec4583a5691375ea32a1d6b)
Signed-off-by: Joel Stanley <joel@jms.id.au>
ARM: dts: aspeed-g4: Add all flash chips2019-09-05T00:52:43+00:00Joel Stanleyjoel@jms.id.au2019-09-05T00:02:20+00:00urn:sha1:9bfa235405e92d676118b7af283b3352271ae326
The FMC supports five chip selects, so describe the five possible flash
chips.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
(cherry picked from commit 901d51435c31f9c3147efa64e379bf00208bde01)
Signed-off-by: Joel Stanley <joel@jms.id.au>
Merge tag 'v5.2.11' into dev-5.22019-09-04T23:39:51+00:00Joel Stanleyjoel@jms.id.au2019-09-04T23:39:44+00:00urn:sha1:f80e773328361320439b4b535ed8fee63ba739ee
This is the 5.2.11 stable release
Signed-off-by: Joel Stanley <joel@jms.id.au>
ARM: dts: ast2600-evb: eMMC configuration2019-09-04T05:07:10+00:00Andrew Jefferyandrew@aj.id.au2019-08-27T07:00:55+00:00urn:sha1:0fd9b646187f638612a3ee5443f8ce0649b6d14b
Enable the eMMC controller and limit it to 52MHz to avoid the host
controller reporting bus error conditions.
OpenBMC-Staging-Count: 1
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>