<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/arm, branch dev-4.3</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.3</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.3'/>
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<updated>2016-02-22T05:16:02+00:00</updated>
<entry>
<title>Remove GPIO and LPC from WDT reset list</title>
<updated>2016-02-22T05:16:02+00:00</updated>
<author>
<name>Norman James</name>
<email>njames@us.ibm.com</email>
</author>
<published>2016-02-18T03:21:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=453106109a92aa265b9041ce0bc667a517000a05'/>
<id>urn:sha1:453106109a92aa265b9041ce0bc667a517000a05</id>
<content type='text'>
WDT reset mode must also be set to SOC mode.  These changes are required
so host is not interrupted when BMC is reboot.  This change will keep
the GPIO and LPC units from being reset during an SOC reset.  The SOC
reset is used to perform a BMC reboot.

Signed-off-by: Norman James &lt;nkskjames@gmail.com&gt;
Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
</content>
</entry>
<entry>
<title>arm: dts: unit address should not have 0x prefix</title>
<updated>2016-02-11T03:00:43+00:00</updated>
<author>
<name>Milton D. Miller II</name>
<email>miltonm@us.ibm.com</email>
</author>
<published>2016-02-11T01:30:28+00:00</published>
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<id>urn:sha1:856ffde999e6366536cc14436fdec4455d05b8db</id>
<content type='text'>
The implied format for most bus bindings implies the uname-address
part of the unit-name should be in hex without a leading 0x.

Fix the one i2c bus that did not follow this convention.

Signed-off-by: Milton Miller &lt;miltonm@us.ibm.com&gt;
Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
</content>
</entry>
<entry>
<title>arm/dts/barreleye: Fix polarity and names of LEDs</title>
<updated>2016-02-10T03:23:49+00:00</updated>
<author>
<name>Norman James</name>
<email>njames@us.ibm.com</email>
</author>
<published>2016-02-05T00:42:01+00:00</published>
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<id>urn:sha1:4b61633e9e65f16b0c1d9d95f585f5f879a5666c</id>
<content type='text'>
Makes names consistent with schematic.

Signed-off-by: Norman James &lt;nkskjames@gmail.com&gt;
Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v4.3.5' into dev-4.3</title>
<updated>2016-02-02T02:23:42+00:00</updated>
<author>
<name>Joel Stanley</name>
<email>joel@jms.id.au</email>
</author>
<published>2016-02-02T02:23:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f3f4aeb9ea8954c0da3cf0d12693f9a57f1f4ac7'/>
<id>urn:sha1:f3f4aeb9ea8954c0da3cf0d12693f9a57f1f4ac7</id>
<content type='text'>
This is the 4.3.5 stable release

Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
</content>
</entry>
<entry>
<title>ARM/arm64: KVM: correct PTE uncachedness check</title>
<updated>2016-01-31T19:25:54+00:00</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ard.biesheuvel@linaro.org</email>
</author>
<published>2015-12-03T08:25:22+00:00</published>
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<id>urn:sha1:d3065fb497d4704de0c653ae3b70c79fd8e2878d</id>
<content type='text'>
commit 0de58f852875a0f0dcfb120bb8433e4e73c7803b upstream.

Commit e6fab5442345 ("ARM/arm64: KVM: test properly for a PTE's
uncachedness") modified the logic to test whether a HYP or stage-2
mapping needs flushing, from [incorrectly] interpreting the page table
attributes to [incorrectly] checking whether the PFN that backs the
mapping is covered by host system RAM. The PFN number is part of the
output of the translation, not the input, so we have to use pte_pfn()
on the contents of the PTE, not __phys_to_pfn() on the HYP virtual
address or stage-2 intermediate physical address.

Fixes: e6fab5442345 ("ARM/arm64: KVM: test properly for a PTE's uncachedness")
Tested-by: Pavel Fedin &lt;p.fedin@samsung.com&gt;
Signed-off-by: Ard Biesheuvel &lt;ard.biesheuvel@linaro.org&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>ARM/arm64: KVM: test properly for a PTE's uncachedness</title>
<updated>2016-01-31T19:25:53+00:00</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ard.biesheuvel@linaro.org</email>
</author>
<published>2015-11-10T14:11:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=b8691782772d00d7761cf298a1cc96420dd107a8'/>
<id>urn:sha1:b8691782772d00d7761cf298a1cc96420dd107a8</id>
<content type='text'>
commit e6fab54423450d699a09ec2b899473a541f61971 upstream.

The open coded tests for checking whether a PTE maps a page as
uncached use a flawed '(pte_val(xxx) &amp; CONST) != CONST' pattern,
which is not guaranteed to work since the type of a mapping is
not a set of mutually exclusive bits

For HYP mappings, the type is an index into the MAIR table (i.e, the
index itself does not contain any information whatsoever about the
type of the mapping), and for stage-2 mappings it is a bit field where
normal memory and device types are defined as follows:

    #define MT_S2_NORMAL            0xf
    #define MT_S2_DEVICE_nGnRE      0x1

I.e., masking *and* comparing with the latter matches on the former,
and we have been getting lucky merely because the S2 device mappings
also have the PTE_UXN bit set, or we would misidentify memory mappings
as device mappings.

Since the unmap_range() code path (which contains one instance of the
flawed test) is used both for HYP mappings and stage-2 mappings, and
considering the difference between the two, it is non-trivial to fix
this by rewriting the tests in place, as it would involve passing
down the type of mapping through all the functions.

However, since HYP mappings and stage-2 mappings both deal with host
physical addresses, we can simply check whether the mapping is backed
by memory that is managed by the host kernel, and only perform the
D-cache maintenance if this is the case.

Signed-off-by: Ard Biesheuvel &lt;ard.biesheuvel@linaro.org&gt;
Tested-by: Pavel Fedin &lt;p.fedin@samsung.com&gt;
Reviewed-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>net: filter: make JITs zero A for SKF_AD_ALU_XOR_X</title>
<updated>2016-01-31T19:25:50+00:00</updated>
<author>
<name>Rabin Vincent</name>
<email>rabin@rab.in</email>
</author>
<published>2016-01-05T15:23:07+00:00</published>
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<id>urn:sha1:a72a87340100097d6d4ad8015014caf7f05442f9</id>
<content type='text'>
[ Upstream commit 55795ef5469290f89f04e12e662ded604909e462 ]

The SKF_AD_ALU_XOR_X ancillary is not like the other ancillary data
instructions since it XORs A with X while all the others replace A with
some loaded value.  All the BPF JITs fail to clear A if this is used as
the first instruction in a filter.  This was found using american fuzzy
lop.

Add a helper to determine if A needs to be cleared given the first
instruction in a filter, and use this in the JITs.  Except for ARM, the
rest have only been compile-tested.

Fixes: 3480593131e0 ("net: filter: get rid of BPF_S_* enum")
Signed-off-by: Rabin Vincent &lt;rabin@rab.in&gt;
Acked-by: Daniel Borkmann &lt;daniel@iogearbox.net&gt;
Acked-by: Alexei Starovoitov &lt;ast@kernel.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>arm/aspeed: Enable VUART driver</title>
<updated>2016-01-30T00:34:20+00:00</updated>
<author>
<name>Jeremy Kerr</name>
<email>jk@ozlabs.org</email>
</author>
<published>2016-01-29T04:55:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=36693bcc928980d718f53aa9d95a840a5da7d5fa'/>
<id>urn:sha1:36693bcc928980d718f53aa9d95a840a5da7d5fa</id>
<content type='text'>
This change makes use of the new VUART device driver. We need a separate
compatible property for the VUART node, and a fix for the interrupt
definitions. We also change the SCU setup to notify host firmware that the
VUART is available.

Signed-off-by: Jeremy Kerr &lt;jk@ozlabs.org&gt;
</content>
</entry>
<entry>
<title>hwmon: Add Power8 OCC hwmon driver</title>
<updated>2016-01-27T06:39:32+00:00</updated>
<author>
<name>Yi Li</name>
<email>adamliyi@msn.com</email>
</author>
<published>2016-01-05T04:10:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=fe68a785afbaa305506c87c6324f70ed0605385c'/>
<id>urn:sha1:fe68a785afbaa305506c87c6324f70ed0605385c</id>
<content type='text'>
Adds a hwmon driver for BMC to monitor Power8 CPU sensors via On Chip
Controller.

Signed-off-by: Yi Li &lt;adamliyi@msn.com&gt;
Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
</content>
</entry>
<entry>
<title>aspeed: update defconfig</title>
<updated>2016-01-27T03:13:54+00:00</updated>
<author>
<name>Milton D. Miller II</name>
<email>miltonm@us.ibm.com</email>
</author>
<published>2016-01-22T02:29:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=0f125e5071a3a65d95277baa77b246c64262cfad'/>
<id>urn:sha1:0f125e5071a3a65d95277baa77b246c64262cfad</id>
<content type='text'>
Turn on the new spi memory controller driver, plus some file systems
that will be used on the new mtd.

Signed-off-by: Milton Miller &lt;miltonm@us.ibm.com&gt;
</content>
</entry>
</feed>
