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<title>BMC/Intel-BMC/linux.git/arch/arm64/include/asm/arch_timer.h, branch dev-4.10</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.10</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev-4.10'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2016-09-23T16:19:25+00:00</updated>
<entry>
<title>arm64: arch_timer: Work around QorIQ Erratum A-008585</title>
<updated>2016-09-23T16:19:25+00:00</updated>
<author>
<name>Scott Wood</name>
<email>oss@buserror.net</email>
</author>
<published>2016-09-22T08:35:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f6dc1576cd517440313c9551b6ffa3d7e389c7c7'/>
<id>urn:sha1:f6dc1576cd517440313c9551b6ffa3d7e389c7c7</id>
<content type='text'>
Erratum A-008585 says that the ARM generic timer counter "has the
potential to contain an erroneous value for a small number of core
clock cycles every time the timer value changes".  Accesses to TVAL
(both read and write) are also affected due to the implicit counter
read.  Accesses to CVAL are not affected.

The workaround is to reread TVAL and count registers until successive
reads return the same value.  Writes to TVAL are replaced with an
equivalent write to CVAL.

The workaround is to reread TVAL and count registers until successive reads
return the same value, and when writing TVAL to retry until counter
reads before and after the write return the same value.

The workaround is enabled if the fsl,erratum-a008585 property is found in
the timer node in the device tree.  This can be overridden with the
clocksource.arm_arch_timer.fsl-a008585 boot parameter, which allows KVM
users to enable the workaround until a mechanism is implemented to
automatically communicate this information.

This erratum can be found on LS1043A and LS2080A.

Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Scott Wood &lt;oss@buserror.net&gt;
[will: renamed read macro to reflect that it's not usually unstable]
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: arch_timer: simplify accessors</title>
<updated>2016-09-09T10:41:13+00:00</updated>
<author>
<name>Mark Rutland</name>
<email>mark.rutland@arm.com</email>
</author>
<published>2016-09-08T12:55:35+00:00</published>
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<id>urn:sha1:cd5f22d7967f613c49288256ce95b07eb910e2a9</id>
<content type='text'>
A while back we added {read,write}_sysreg accessors to handle accesses
to system registers, without the usual boilerplate asm volatile,
temporary variable, etc.

This patch makes use of these in the arm64 arch timer accessors to make
the code shorter and clearer.

Signed-off-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: fix missing linux/bug.h include in asm/arch_timer.h</title>
<updated>2015-01-07T11:40:59+00:00</updated>
<author>
<name>Paul Walmsley</name>
<email>pwalmsley@nvidia.com</email>
</author>
<published>2015-01-06T00:38:41+00:00</published>
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<id>urn:sha1:082471a8efe1a91d4e44abec202d9e3067dcec91</id>
<content type='text'>
On next-20150105, defconfig compilation breaks with:

./arch/arm64/include/asm/arch_timer.h:112:2: error: implicit declaration of function ‘BUG’ [-Werror=implicit-function-declaration]

Fix by including linux/bug.h, where the BUG macro is defined.

This second version incorporates a comment from Mark Rutland
&lt;mark.rutland@arm.com&gt; to keep the includes in alphabetical order
by filename.

Signed-off-by: Paul Walmsley &lt;paul@pwsan.com&gt;
Cc: Paul Walmsley &lt;pwalmsley@nvidia.com&gt;
Cc: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Acked-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>clocksource: arch_timer: Fix code to use physical timers when requested</title>
<updated>2014-12-05T07:30:26+00:00</updated>
<author>
<name>Sonny Rao</name>
<email>sonnyrao@chromium.org</email>
</author>
<published>2014-11-24T07:02:44+00:00</published>
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<id>urn:sha1:0b46b8a718c6e90910a1b1b0fe797be3c167e186</id>
<content type='text'>
This is a bug fix for using physical arch timers when
the arch_timer_use_virtual boolean is false.  It restores the
arch_counter_get_cntpct() function after removal in

0d651e4e "clocksource: arch_timer: use virtual counters"

We need this on certain ARMv7 systems which are architected like this:

* The firmware doesn't know and doesn't care about hypervisor mode and
  we don't want to add the complexity of hypervisor there.

* The firmware isn't involved in SMP bringup or resume.

* The ARCH timer come up with an uninitialized offset between the
  virtual and physical counters.  Each core gets a different random
  offset.

* The device boots in "Secure SVC" mode.

* Nothing has touched the reset value of CNTHCTL.PL1PCEN or
  CNTHCTL.PL1PCTEN (both default to 1 at reset)

One example of such as system is RK3288 where it is much simpler to
use the physical counter since there's nobody managing the offset and
each time a core goes down and comes back up it will get reinitialized
to some other random value.

Fixes: 0d651e4e65e9 ("clocksource: arch_timer: use virtual counters")
Cc: stable@vger.kernel.org
Signed-off-by: Sonny Rao &lt;sonnyrao@chromium.org&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>clocksource: arm_arch_timer: Consolidate arch_timer_evtstrm_enable</title>
<updated>2014-09-28T23:59:26+00:00</updated>
<author>
<name>Nathan Lynch</name>
<email>nathan_lynch@mentor.com</email>
</author>
<published>2014-09-28T23:50:06+00:00</published>
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<id>urn:sha1:e1ce5c7adc735ce96a35806ca32ceb78e607a283</id>
<content type='text'>
The arch_timer_evtstrm_enable hooks in arm and arm64 are substantially
similar, the only difference being a CONFIG_COMPAT-conditional section
which is relevant only for arm64.  Copy the arm64 version to the
driver, removing the arch-specific hooks.

Signed-off-by: Nathan Lynch &lt;nathan_lynch@mentor.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>clocksource: arm_arch_timer: Enable counter access for 32-bit ARM</title>
<updated>2014-09-28T23:59:25+00:00</updated>
<author>
<name>Nathan Lynch</name>
<email>nathan_lynch@mentor.com</email>
</author>
<published>2014-09-28T23:50:06+00:00</published>
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<id>urn:sha1:8b8dde00347ef409b29abd97e5833ffdb4ed7508</id>
<content type='text'>
The only difference between arm and arm64's implementations of
arch_counter_set_user_access is that 32-bit ARM does not enable user
access to the virtual counter.  We want to enable this access for the
32-bit ARM VDSO, so copy the arm64 version to the driver itself, and
remove the arch-specific implementations.

Signed-off-by: Nathan Lynch &lt;nathan_lynch@mentor.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>ARM64: arch_timer: add support to configure and enable event stream</title>
<updated>2013-09-26T08:47:43+00:00</updated>
<author>
<name>Sudeep KarkadaNagesha</name>
<email>sudeep.karkadanagesha@arm.com</email>
</author>
<published>2013-08-13T14:57:53+00:00</published>
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<id>urn:sha1:46efe547aca8498d51b64460c02366ae4032ca32</id>
<content type='text'>
This patch adds support for configuring the event stream frequency
and enabling it.

It also adds the hwcaps as well as compat-specific definitions to
the user to detect this event stream feature.

Cc: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Olof Johansson &lt;olof@lixom.net&gt;
Signed-off-by: Sudeep KarkadaNagesha &lt;sudeep.karkadanagesha@arm.com&gt;
</content>
</entry>
<entry>
<title>ARM/ARM64: arch_timer: add macros for bits in control register</title>
<updated>2013-09-26T08:47:06+00:00</updated>
<author>
<name>Sudeep KarkadaNagesha</name>
<email>sudeep.karkadanagesha@arm.com</email>
</author>
<published>2013-08-13T12:43:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=28061758dc83df445a05af347b5ce55ccd968c03'/>
<id>urn:sha1:28061758dc83df445a05af347b5ce55ccd968c03</id>
<content type='text'>
Add macros to describe the bitfields in the ARM architected timer
control register to make code easy to understand.

Reviewed-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Will Deacon &lt;will.deacon@arm.com&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Olof Johansson &lt;olof@lixom.net&gt;
Signed-off-by: Sudeep KarkadaNagesha &lt;sudeep.karkadanagesha@arm.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'timers/clockevents-next' of git://git.linaro.org/people/dlezcano/clockevents into timers/core</title>
<updated>2013-08-21T12:59:23+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2013-08-21T12:59:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=cfb6d656d569510ac9239583ce09e4c92ad54719'/>
<id>urn:sha1:cfb6d656d569510ac9239583ce09e4c92ad54719</id>
<content type='text'>
* Support for memory mapped arch_timers
* Trivial fixes to the moxart timer code
* Documentation updates

Trivial conflicts in drivers/clocksource/arm_arch_timer.c. Fixed up
the newly added __cpuinit annotations as well.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>clocksource: arch_timer: Push the read/write wrappers deeper</title>
<updated>2013-07-31T23:13:37+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2013-07-18T23:59:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=60faddf6eb3aba16068032bdcf35e18ace4bfb21'/>
<id>urn:sha1:60faddf6eb3aba16068032bdcf35e18ace4bfb21</id>
<content type='text'>
We're going to introduce support to read and write the memory
mapped timer registers in the next patch, so push the cp15
read/write functions one level deeper. This simplifies the next
patch and makes it clearer what's going on.

Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Marc Zyngier &lt;Marc.Zyngier@arm.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Acked-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
</content>
</entry>
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