<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/arm64/boot/dts/arm, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2015-07-08T21:44:56+00:00</updated>
<entry>
<title>arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG</title>
<updated>2015-07-08T21:44:56+00:00</updated>
<author>
<name>Kristina Martsenko</name>
<email>kristina.martsenko@arm.com</email>
</author>
<published>2015-07-01T12:36:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=9ccd608070b6d4fd1a89fd76a84184fe401fb6a8'/>
<id>urn:sha1:9ccd608070b6d4fd1a89fd76a84184fe401fb6a8</id>
<content type='text'>
Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented
on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on
the version that's currently available from the ARM DTS repository [1].

[1] git://linux-arm.org/arm-dts.git

Signed-off-by: Kristina Martsenko &lt;kristina.martsenko@arm.com&gt;
Acked-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
Signed-off-by: Kevin Hilman &lt;khilman@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2015-06-26T18:54:29+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2015-06-26T18:54:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=f5dcb68086ba2e033b2af32b0da0c7a7c7872a09'/>
<id>urn:sha1:f5dcb68086ba2e033b2af32b0da0c7a7c7872a09</id>
<content type='text'>
Pull ARM SoC driver updates from Kevin Hilman:
 "Some of these are for drivers/soc, where we're now putting
  SoC-specific drivers these days.  Some are for other driver subsystems
  where we have received acks from the appropriate maintainers.

  Some highlights:

   - simple-mfd: document DT bindings and misc updates
   - migrate mach-berlin to simple-mfd for clock, pinctrl and reset
   - memory: support for Tegra132 SoC
   - memory: introduce tegra EMC driver for scaling memory frequency
   - misc. updates for ARM CCI and CCN busses"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
  drivers: soc: sunxi: Introduce SoC driver to map SRAMs
  arm-cci: Add aliases for PMU events
  arm-cci: Add CCI-500 PMU support
  arm-cci: Sanitise CCI400 PMU driver specific code
  arm-cci: Abstract handling for CCI events
  arm-cci: Abstract out the PMU counter details
  arm-cci: Cleanup PMU driver code
  arm-cci: Do not enable CCI-400 PMU by default
  firmware: qcom: scm: Add HDCP Support
  ARM: berlin: add an ADC node for the BG2Q
  ARM: berlin: remove useless chip and system ctrl compatibles
  clk: berlin: drop direct of_iomap of nodes reg property
  ARM: berlin: move BG2Q clock node
  ARM: berlin: move BG2CD clock node
  ARM: berlin: move BG2 clock node
  clk: berlin: prepare simple-mfd conversion
  pinctrl: berlin: drop SoC stub provided regmap
  ARM: berlin: move pinctrl to simple-mfd nodes
  pinctrl: berlin: prepare to use regmap provided by syscon
  reset: berlin: drop arch_initcall initialization
  ...
</content>
</entry>
<entry>
<title>Merge tag 'v4.1-rc6' into next/dt</title>
<updated>2015-06-11T21:37:45+00:00</updated>
<author>
<name>Kevin Hilman</name>
<email>khilman@linaro.org</email>
</author>
<published>2015-06-11T21:37:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=ecdf94da6f91310d08081e05db78a6c997b44e4b'/>
<id>urn:sha1:ecdf94da6f91310d08081e05db78a6c997b44e4b</id>
<content type='text'>
Linux 4.1-rc6

 Conflicts:
	arch/arm/boot/dts/zynq-7000.dtsi

Resolution summary:

 Mainline had an earlier version of the commit, resolve in favor of the
 newer patch in next/dt branch.
</content>
</entry>
<entry>
<title>ARM64: juno: add GPIO keys</title>
<updated>2015-06-11T21:15:05+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2015-06-04T11:41:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=53bdd72c68f0861d57851232c14a5750779b368b'/>
<id>urn:sha1:53bdd72c68f0861d57851232c14a5750779b368b</id>
<content type='text'>
The Juno board has two keys connected to a PL061 GPIO block,
in accordance to DDI0524B "ARM Versatile Express Juno Development
Platform" revision 1.0, table 2-4 "GPIO (0) and GPIO (1) used
for additional user key entry". By trial-and-error I found that
these are connected to the two keys named "power" and "home"
on the motherboard.

Register the GPIO block and these two keys in the device tree
using the PL061 GPIO driver and the generic gpio keys.

- Map POWER, HOME, VOL+ and VOL- to the obvious input events.
- Map RLOCK to KEY_SCREENLOCK/KEY_COFFEE unless someone can
  explain better what this is for.
- Map the NMI button to KEY_SYSREQ as this is used like so
  in the SYSREQ debugging hack.

Acked-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: Add DT support for Juno r1 board.</title>
<updated>2015-05-22T15:25:35+00:00</updated>
<author>
<name>Liviu Dudau</name>
<email>Liviu.Dudau@arm.com</email>
</author>
<published>2015-03-10T15:31:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=796c2b35a4105aa02c6a7af6de659086363d47f7'/>
<id>urn:sha1:796c2b35a4105aa02c6a7af6de659086363d47f7</id>
<content type='text'>
This board is based on Juno r0 with updated Cortex A5x revisions
and board errata fixes. It also contains coherent ThinLinks ports
on the expansion slot that allow for an AXI master on the daughter
card to participate in a coherency domain.

Support for SoC PCIe host bridge will be added as a separate series.

Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
Acked-by: Jon Medhurst &lt;tixy@linaro.org&gt;
Acked-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: Juno: Add GICv2m support in device tree.</title>
<updated>2015-05-22T15:25:31+00:00</updated>
<author>
<name>Liviu Dudau</name>
<email>Liviu.Dudau@arm.com</email>
</author>
<published>2015-03-26T12:16:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=9e6f374f99a0c83c6f58cb6f6356645ef8591d1e'/>
<id>urn:sha1:9e6f374f99a0c83c6f58cb6f6356645ef8591d1e</id>
<content type='text'>
Juno contains a GICv2m extension for handling PCIe MSI messages.
Add a node declaring the first frame of the extension.

Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
Acked-by: Jon Medhurst &lt;tixy@linaro.org&gt;
Acked-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: Juno: Add memory mapped timer node</title>
<updated>2015-05-22T15:25:25+00:00</updated>
<author>
<name>Liviu Dudau</name>
<email>Liviu.Dudau@arm.com</email>
</author>
<published>2015-03-10T15:21:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=7950235568dad46683e14aa36678366b43e56fac'/>
<id>urn:sha1:7950235568dad46683e14aa36678366b43e56fac</id>
<content type='text'>
Juno based boards have a memory mapped timer @ 0x2a810000. This
is disabled on r0 version of the board due to an SoC errata.

Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
Acked-by: Jon Medhurst &lt;tixy@linaro.org&gt;
Acked-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: Juno: Split juno.dts into juno-base.dtsi and juno.dts.</title>
<updated>2015-05-22T15:25:16+00:00</updated>
<author>
<name>Liviu Dudau</name>
<email>Liviu.Dudau@arm.com</email>
</author>
<published>2015-03-10T15:18:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=e802087437c120b2bf0f213aba5c88c175d7019c'/>
<id>urn:sha1:e802087437c120b2bf0f213aba5c88c175d7019c</id>
<content type='text'>
Prepare the device tree for adding more boards based on Juno r0.

Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
Acked-by: Jon Medhurst &lt;tixy@linaro.org&gt;
Acked-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: Juno: Fix the GIC node address label and the frequency of FAXI clock.</title>
<updated>2015-05-22T15:25:07+00:00</updated>
<author>
<name>Liviu Dudau</name>
<email>Liviu.Dudau@arm.com</email>
</author>
<published>2015-04-30T15:45:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=18c0b015305edd97c2b31e0ce7211a960d08f62f'/>
<id>urn:sha1:18c0b015305edd97c2b31e0ce7211a960d08f62f</id>
<content type='text'>
During the review of the Juno DT files I've noticed that the GIC
node label had two digits swapped leading to a different address
being shown in the /sys/devices fs.

Sudeep also pointed that public revisions of the Juno documentation
list a different frequency for the FAXI system than what the one
I've been using when creating the DT file. Verified with the firmware
people to be the correct value in the shipped systems.

Reported-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
Acked-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
Acked-by: Jon Medhurst &lt;tixy@linaro.org&gt;
</content>
</entry>
<entry>
<title>ARM64: juno: add sp810 support and fix sp804 clock frequency</title>
<updated>2015-05-12T14:39:28+00:00</updated>
<author>
<name>Sudeep Holla</name>
<email>sudeep.holla@arm.com</email>
</author>
<published>2015-05-07T14:45:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=3bb1555c0d2df5b84da12d2b639aa89c45d141aa'/>
<id>urn:sha1:3bb1555c0d2df5b84da12d2b639aa89c45d141aa</id>
<content type='text'>
The clock generator in IOFPGA generates the two source clocks: 32kHz and
1MHz for the SP810 System Controller.

The SP810 System Controller selects 32kHz or 1MHz as the sources for
TIM_CLK[3:0], the SP804 timer clocks. The powerup default is 32kHz but
the maximum of "refclk" and "timclk" is chosen by the SP810 driver.

This patch adds support for SP810 system controller and also fixes the
SP804 timer clock frequency.

However the SP804 driver needs to be enabled on ARM64 to test this,
which requires SP804 driver to be moved out of arch/arm.

Fixes: 71f867ec130e ("arm64: Add Juno board device tree.")
Cc: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Olof Johansson &lt;olof@lixom.net&gt;
Acked-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
</feed>
