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<title>BMC/Intel-BMC/linux.git/arch/arm/mm/flush.c, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
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<updated>2014-12-03T16:00:04+00:00</updated>
<entry>
<title>ARM: 8237/1: fix flush_pfn_alias</title>
<updated>2014-12-03T16:00:04+00:00</updated>
<author>
<name>Jungseung Lee</name>
<email>js07.lee@gmail.com</email>
</author>
<published>2014-11-29T01:54:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=12e669b4874274caaefd20d3c729471b8ebe8d93'/>
<id>urn:sha1:12e669b4874274caaefd20d3c729471b8ebe8d93</id>
<content type='text'>
L1_CACHE_BYTES could be larger than real L1 cache line size.
In that case, flush_pfn_alias() would omit to flush last bytes
as much as L1_CACHE_BYTES - real cache line size.

So fix end address to "to + PAGE_SIZE - 1". The bottom bits of the address
is LINELEN. that is ignored by mcrr.

Signed-off-by: Jungseung Lee &lt;js07.lee@gmail.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>arm: mm: enable RCU fast_gup</title>
<updated>2014-10-10T02:26:01+00:00</updated>
<author>
<name>Steve Capper</name>
<email>steve.capper@linaro.org</email>
</author>
<published>2014-10-09T22:29:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=b8cd51afe05a98ef907e61c603d5c5b7ad6242d8'/>
<id>urn:sha1:b8cd51afe05a98ef907e61c603d5c5b7ad6242d8</id>
<content type='text'>
Activate the RCU fast_gup for ARM.  We also need to force THP splits to
broadcast an IPI s.t.  we block in the fast_gup page walker.  As THP
splits are comparatively rare, this should not lead to a noticeable
performance degradation.

Some pre-requisite functions pud_write and pud_page are also added.

Signed-off-by: Steve Capper &lt;steve.capper@linaro.org&gt;
Reviewed-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Cc: Dann Frazier &lt;dann.frazier@canonical.com&gt;
Cc: Hugh Dickins &lt;hughd@google.com&gt;
Cc: Russell King &lt;rmk@arm.linux.org.uk&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Mel Gorman &lt;mel@csn.ul.ie&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Cc: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Cc: Andrea Arcangeli &lt;aarcange@redhat.com&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>ARM: 8043/1: uprobes need icache flush after xol write</title>
<updated>2014-05-25T22:48:45+00:00</updated>
<author>
<name>Victor Kamensky</name>
<email>victor.kamensky@linaro.org</email>
</author>
<published>2014-04-29T03:20:52+00:00</published>
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<id>urn:sha1:72e6ae285a1dbff553734985bedadf409d99c02d</id>
<content type='text'>
After instruction write into xol area, on ARM V7
architecture code need to flush dcache and icache to sync
them up for given set of addresses. Having just
'flush_dcache_page(page)' call is not enough - it is
possible to have stale instruction sitting in icache
for given xol area slot address.

Introduce arch_uprobe_ixol_copy weak function
that by default calls uprobes copy_to_page function and
than flush_dcache_page function and on ARM define new one
that handles xol slot copy in ARM specific way

flush_uprobe_xol_access function shares/reuses implementation
with/of flush_ptrace_access function and takes care of writing
instruction to user land address space on given variety of
different cache types on ARM CPUs. Because
flush_uprobe_xol_access does not have vma around
flush_ptrace_access was split into two parts. First that
retrieves set of condition from vma and common that receives
those conditions as flags.

Note ARM cache flush function need kernel address
through which instruction write happened, so instead
of using uprobes copy_to_page function changed
code to explicitly map page and do memcpy.

Note arch_uprobe_copy_ixol function, in similar way as
copy_to_user_page function, has preempt_disable/preempt_enable.

Signed-off-by: Victor Kamensky &lt;victor.kamensky@linaro.org&gt;
Acked-by: Oleg Nesterov &lt;oleg@redhat.com&gt;
Reviewed-by: David A. Long &lt;dave.long@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: 7923/1: mm: fix dcache flush logic for compound high pages</title>
<updated>2013-12-29T12:46:08+00:00</updated>
<author>
<name>Steven Capper</name>
<email>steve.capper@linaro.org</email>
</author>
<published>2013-12-16T16:25:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=2a7cfcbc0553365d75716f69ee7b704cac7c9248'/>
<id>urn:sha1:2a7cfcbc0553365d75716f69ee7b704cac7c9248</id>
<content type='text'>
When given a compound high page, __flush_dcache_page will only flush
the first page of the compound page repeatedly rather than the entire
set of constituent pages.

This error was introduced by:
   0b19f93 ARM: mm: Add support for flushing HugeTLB pages.

This patch corrects the logic such that all constituent pages are now
flushed.

Cc: stable@vger.kernel.org # 3.10+
Signed-off-by: Steve Capper &lt;steve.capper@linaro.org&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>Merge branch 'devel-stable' into for-next</title>
<updated>2013-06-29T10:44:43+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2013-06-29T10:44:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=3c0c01ab742ddfaf6b6f2d64b890e77cda4b7727'/>
<id>urn:sha1:3c0c01ab742ddfaf6b6f2d64b890e77cda4b7727</id>
<content type='text'>
Conflicts:
	arch/arm/Makefile
	arch/arm/include/asm/glue-proc.h
</content>
</entry>
<entry>
<title>Merge branches 'fixes', 'mcpm', 'misc' and 'mmci' into for-next</title>
<updated>2013-06-29T10:43:28+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2013-06-29T10:43:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=cbd379b10019617457bda31eb243890f4377fa3e'/>
<id>urn:sha1:cbd379b10019617457bda31eb243890f4377fa3e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: 7755/1: handle user space mapped pages in flush_kernel_dcache_page</title>
<updated>2013-06-17T09:30:52+00:00</updated>
<author>
<name>Simon Baatz</name>
<email>gmbnomis@gmail.com</email>
</author>
<published>2013-06-10T20:10:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=1bc39742aab09248169ef9d3727c9def3528b3f3'/>
<id>urn:sha1:1bc39742aab09248169ef9d3727c9def3528b3f3</id>
<content type='text'>
Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that
the pages it needs to handle are kernel mapped only.  However, for
example when doing direct I/O, pages with user space mappings may
occur.

Thus, continue to do lazy flushing if there are no user space
mappings.  Otherwise, flush the kernel cache lines directly.

Signed-off-by: Simon Baatz &lt;gmbnomis@gmail.com&gt;
Reviewed-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # 3.2+
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: 7746/1: mm: lazy cache flushing on non-mapped pages</title>
<updated>2013-06-05T22:37:32+00:00</updated>
<author>
<name>Ming Lei</name>
<email>tom.leiming@gmail.com</email>
</author>
<published>2013-06-05T01:44:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=81f28946a8b066d484ca8935ff545d94ce730aa3'/>
<id>urn:sha1:81f28946a8b066d484ca8935ff545d94ce730aa3</id>
<content type='text'>
Currently flush_dcache_page() thinks pages as non-mapped if
mapping_mapped(mapping) return false. This approach is very
coase:
	- mmap on part of file may cause all pages backed on
	the file being thought as mmaped

	- file-backed pages aren't mapped into user space actually
	if the memory mmaped on the file isn't accessed

This patch uses page_mapped() to decide if the page has been
mapped.

From the attached test code, I find there is much performance
improvement(&gt;25%) when accessing page caches via read under this
situations, so memcpy benefits a lot from not flushing cache
under this situation.

No.   read time without the patch	No. read time with the patch
================================================================
No. 0, time  22615636 us		No. 0, time  22014717 us
No. 1, time  4387851 us 		No. 1, time  3113184 us
No. 2, time  4276535 us 		No. 2, time  3005244 us
No. 3, time  4259821 us 		No. 3, time  3001565 us
No. 4, time  4263811 us 		No. 4, time  3002748 us
No. 5, time  4258486 us 		No. 5, time  3004104 us
No. 6, time  4253009 us 		No. 6, time  3002188 us
No. 7, time  4262809 us 		No. 7, time  2998196 us
No. 8, time  4264525 us 		No. 8, time  3007255 us
No. 9, time  4267795 us 		No. 9, time  3005094 us

1), No.0. is to read the file from storage device, and others are
to read the file from page caches basically.
2), file size is 512M, and is on ext4 over usb mass storage.
3), the test is done on Pandaboard.

unsigned int  sum = 0;
unsigned long sum_val = 0;

static unsigned long tv_diff(struct timeval *tv1, struct timeval *tv2)
{
	return (tv2-&gt;tv_sec - tv1-&gt;tv_sec) * 1000000 +
		(tv2-&gt;tv_usec - tv1-&gt;tv_usec);
}

int main(int argc, char *argv[])
{
	char *mbuf, fbuf;
	int fd;
	int i;
	unsigned long page_size, size;
	struct stat stat;
	struct timeval t1, t2;
	unsigned char *rbuf = malloc(32 * page_size);

	if (!rbuf) {
		printf("	%sn", "malloc failed");
		exit(-1);
	}

	page_size = getpagesize();
	fd = open(argv[1], O_RDWR);
	assert(fd &gt;= 0);

	fstat(fd, &amp;stat);
	size = stat.st_size;
	printf("%s: file %s, size %lu, page size %lun",
		argv[0],
		argv[1], size, page_size);

	gettimeofday(&amp;t1, NULL);
	mbuf = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
	if (!mbuf) {
		printf("	%sn", "mmap failed");
		exit(-1);
	}

	for (i = 0 ; i &lt; size ; i += (page_size * 32)) {
		int rcnt;
		lseek(fd, i, SEEK_SET);
		rcnt = read(fd, rbuf, page_size * 32);
		if (rcnt != page_size * 32) {
			printf("%s: read faildn", __func__);
			exit(-1);
		}
	}
	free(rbuf);
	munmap(mbuf, size);
	gettimeofday(&amp;t2, NULL);
	printf("tread mmaped time: %luusn", tv_diff(&amp;t1, &amp;t2));

	close(fd);
}

Cc: Michel Lespinasse &lt;walken@google.com&gt;
Cc: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Cc: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Reviewed-by: Will Deacon &lt;will.deacon@arm.com&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Ming Lei &lt;ming.lei@canonical.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: mm: Add support for flushing HugeTLB pages.</title>
<updated>2013-06-04T15:52:37+00:00</updated>
<author>
<name>Steve Capper</name>
<email>steve.capper@linaro.org</email>
</author>
<published>2013-05-17T11:33:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=0b19f93351dd68cb68a1a5b2d74e13d2ddfcfc64'/>
<id>urn:sha1:0b19f93351dd68cb68a1a5b2d74e13d2ddfcfc64</id>
<content type='text'>
On ARM we use the __flush_dcache_page function to flush the dcache
of pages when needed; usually when the PG_dcache_clean bit is unset
and we are setting a PTE.

A HugeTLB page is represented as a compound page consisting of an
array of pages. Thus to flush the dcache of a HugeTLB page, one must
flush more than a single page.

This patch modifies __flush_dcache_page such that all constituent
pages of a HugeTLB page are flushed.

Signed-off-by: Steve Capper &lt;steve.capper@linaro.org&gt;
Reviewed-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>ARM: 7693/1: mm: clean-up in order to reduce to call kmap_high_get()</title>
<updated>2013-04-17T15:55:01+00:00</updated>
<author>
<name>Joonsoo Kim</name>
<email>iamjoonsoo.kim@lge.com</email>
</author>
<published>2013-04-05T02:16:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=dd0f67f4747797f36f0c6bab7fed6a1f2448476d'/>
<id>urn:sha1:dd0f67f4747797f36f0c6bab7fed6a1f2448476d</id>
<content type='text'>
In kmap_atomic(), kmap_high_get() is invoked for checking already
mapped area. In __flush_dcache_page() and dma_cache_maint_page(),
we explicitly call kmap_high_get() before kmap_atomic()
when cache_is_vipt(), so kmap_high_get() can be invoked twice.
This is useless operation, so remove one.

v2: change cache_is_vipt() to cache_is_vipt_nonaliasing() in order to
be self-documented

Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Signed-off-by: Joonsoo Kim &lt;iamjoonsoo.kim@lge.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
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