Intel OpenBMC Linux kernel source tree (mirror) https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev 2015-06-12T20:18:08+00:00 2015-06-12T20:18:08+00:00 Russell King rmk+kernel@arm.linux.org.uk 2015-06-12T20:18:08+00:00 urn:sha1:9de44aa4dc969e4a46c2bfbd33d65bfa6ad2a15d 2015-06-01T22:46:33+00:00 Russell King rmk+kernel@arm.linux.org.uk 2015-04-04T15:58:38+00:00 urn:sha1:d8dc7fbd53eeb329a1dda5a19df7058b9c1c413e Re-implement the physical address space switching to be architecturally compliant. This involves flushing the caches, disabling the MMU, and only then updating the page tables. Once that is complete, the system can be brought back up again. Since we disable the MMU, we need to do the update in assembly code. Luckily, the entries which need updating are fairly trivial, and are all setup by the early assembly code. We can merely adjust each entry by the delta required. Not only does this fix the code to be architecturally compliant, but it fixes a couple of bugs too: 1. The original code would only ever update the first L2 entry covering a fraction of the kernel; the remainder were left untouched. 2. The L2 entries covering the DTB blob were likewise untouched. This solution fixes up all entries. Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2015-05-27T23:29:22+00:00 Arnd Bergmann arnd@arndb.de 2015-05-26T15:10:02+00:00 urn:sha1:90543ec8290b31b15fc9dd6de8e9c2b6347a9059 The feroceon copypage implementation cannot be built when targetting an ARMv4 CPU, so we need to pass the march=armv5te flag manually to gcc when building this file. This is obviously safe since that code will not be executed on ARMv4. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2014-12-03T16:00:05+00:00 Jungseung Lee js07.lee@gmail.com 2014-11-29T02:02:11+00:00 urn:sha1:4e802cfd74e6351cb937997996de9ca2e67df9f2 set_memory_* functions have same implementation except memory attribute. This patch makes to use common function for these, and pull out the functions into arch/arm/mm/pageattr.c like arm64 did. It will reduce code size and enhance the readability. Signed-off-by: Jungseung Lee <js07.lee@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2014-05-29T23:49:01+00:00 Russell King rmk+kernel@arm.linux.org.uk 2014-04-05T10:39:57+00:00 urn:sha1:de7e75326c05c10ebd96aed9440c870f0ff1e34f Provide a common assembly implementation for PL310 resume code. Certain platforms need to re-initialise the L2C cache early as it may preserve data across a S2RAM cycle, and therefore must be enabled along with the L1 cache and MMU. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2014-05-29T23:47:23+00:00 Russell King rmk+kernel@arm.linux.org.uk 2014-03-16T13:14:38+00:00 urn:sha1:1f1d5b745a4617a2cb2ffd8f4a9bc3be664cfc98 Add WARN_ON() conditions to outer_disable() to ensure that its requirements aren't violated. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2013-12-11T09:53:13+00:00 Russell King rmk+kernel@arm.linux.org.uk 2013-10-23T15:13:02+00:00 urn:sha1:1fd15b879d0075c8916e52fb9e52522827433d1f This patch allows the kernel page tables to be dumped via a debugfs file, allowing kernel developers to check the layout of the kernel page tables and the verify the various permissions and type settings. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2013-06-18T19:05:48+00:00 Russell King rmk+kernel@arm.linux.org.uk 2013-06-18T19:03:30+00:00 urn:sha1:b3f288de7c8add67a3364e989b865b6537838662 These changes bring both HugeTLB support and Transparent HugePage (THP) support to ARM. Only long descriptors (LPAE) are supported in this series. The code has been tested on an Arndale board (Exynos 5250). 2013-06-04T15:52:37+00:00 Catalin Marinas catalin.marinas@arm.com 2012-07-25T13:32:38+00:00 urn:sha1:1355e2a6eb88f04d76125c057dc5fca64d4b6a9e This patch adds support for hugetlbfs based on the x86 implementation. It allows mapping of 2MB sections (see Documentation/vm/hugetlbpage.txt for usage). The 64K pages configuration is not supported (section size is 512MB in this case). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> [steve.capper@linaro.org: symbolic constants replace numbers in places. Split up into multiple files, to simplify future non-LPAE support, removed huge_pmd_share code, as this is very rarely executed, Added PROT_NONE support]. Signed-off-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Will Deacon <will.deacon@arm.com> 2013-05-22T09:52:24+00:00 Russell King rmk+kernel@arm.linux.org.uk 2013-05-19T00:22:53+00:00 urn:sha1:f150abe1012f2fc7d444d33d651db32435038c11 Pull ARM-v7M support from Uwe Kleine-König: "All but the last patch were in next since next-20130418 without issues. The last patch fixes a problem in combination with 8164f7a (ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register) which triggers a WARN_ON without an implemented read_cpuid_ext. The branch merges fine into v3.10-rc1 and I'd be happy if you pulled it for 3.11-rc1. The only missing piece to be able to run a Cortex-M3 is the irqchip driver that will go in via Thomas Gleixner and platform specific stuff."