<feed xmlns='http://www.w3.org/2005/Atom'>
<title>BMC/Intel-BMC/linux.git/arch/arm/mm/Kconfig, branch dev</title>
<subtitle>Intel OpenBMC Linux kernel source tree (mirror)</subtitle>
<id>https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev</id>
<link rel='self' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/'/>
<updated>2015-06-12T20:18:08+00:00</updated>
<entry>
<title>Merge branches 'arnd-fixes', 'clk', 'misc', 'v7' and 'fixes' into for-next</title>
<updated>2015-06-12T20:18:08+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2015-06-12T20:18:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=9de44aa4dc969e4a46c2bfbd33d65bfa6ad2a15d'/>
<id>urn:sha1:9de44aa4dc969e4a46c2bfbd33d65bfa6ad2a15d</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: 8369/1: ARMv7M: define size of vector table for Vybrid</title>
<updated>2015-06-02T08:58:19+00:00</updated>
<author>
<name>Stefan Agner</name>
<email>stefan@agner.ch</email>
</author>
<published>2015-05-19T23:16:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=45b0fa09c6e47c02ac0a08bd2b3c6a73480222e0'/>
<id>urn:sha1:45b0fa09c6e47c02ac0a08bd2b3c6a73480222e0</id>
<content type='text'>
Vybrids has 112 peripheral interrupts which can be routed to the
Cortex-M4's NVIC interrupt controller.

Signed-off-by: Stefan Agner &lt;stefan@agner.ch&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: re-implement physical address space switching</title>
<updated>2015-06-01T22:46:33+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2015-04-04T15:58:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=d8dc7fbd53eeb329a1dda5a19df7058b9c1c413e'/>
<id>urn:sha1:d8dc7fbd53eeb329a1dda5a19df7058b9c1c413e</id>
<content type='text'>
Re-implement the physical address space switching to be architecturally
compliant.  This involves flushing the caches, disabling the MMU, and
only then updating the page tables.  Once that is complete, the system
can be brought back up again.

Since we disable the MMU, we need to do the update in assembly code.
Luckily, the entries which need updating are fairly trivial, and are
all setup by the early assembly code.  We can merely adjust each entry
by the delta required.

Not only does this fix the code to be architecturally compliant, but it
fixes a couple of bugs too:

1. The original code would only ever update the first L2 entry covering
   a fraction of the kernel; the remainder were left untouched.
2. The L2 entries covering the DTB blob were likewise untouched.

This solution fixes up all entries.

Tested-by: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: 8374/1: no longer expose CPU_ARM7TDMI/CPU_ARM9TDMI</title>
<updated>2015-05-27T23:29:14+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2015-05-26T14:40:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=c32b76557287a032d1a38032f55c50d3a27dc743'/>
<id>urn:sha1:c32b76557287a032d1a38032f55c50d3a27dc743</id>
<content type='text'>
Atmel at91x40 is gone, so we no longer have any platform using
either of these two, and we get randconfig failures on NOMMU
kernels if they accidentally get enabled on something that conflicts
with ARMv4T.

This stops short of removing the entire CPU support for now,
but as nothing selects these, it is basically dead code.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: 8340/1: ARMv7-M: Enlarge vector table up to 256 entries</title>
<updated>2015-05-08T09:42:21+00:00</updated>
<author>
<name>Maxime Coquelin stm32</name>
<email>mcoquelin.stm32@gmail.com</email>
</author>
<published>2015-04-10T08:46:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=6b1814cde5c79c6aa4d02c9aedc14a709c2c0737'/>
<id>urn:sha1:6b1814cde5c79c6aa4d02c9aedc14a709c2c0737</id>
<content type='text'>
From Cortex-M reference manuals, the nvic supports up to 240 interrupts.
So the number of entries in vectors table is up to 256.

This patch adds a new config flag to specify the number of external interrupts.
Some ifdeferies are added in order to respect the natural alignment without
wasting too much space on smaller systems.

Acked-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Acked-by: Stefan Agner &lt;stefan@agner.ch&gt;
Tested-by: Chanwoo Choi &lt;cw00.choi@samsung.com&gt;
Signed-off-by: Maxime Coquelin &lt;mcoquelin.stm32@gmail.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>Merge branches 'misc' and 'vdso' into for-next</title>
<updated>2015-04-23T21:05:16+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2015-04-23T21:05:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=6b7acae74fc2ffe6cfd7592e95ca933cadb31219'/>
<id>urn:sha1:6b7acae74fc2ffe6cfd7592e95ca933cadb31219</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: 8342/1: VDSO: depend on CPU_V7</title>
<updated>2015-04-17T23:23:25+00:00</updated>
<author>
<name>Nathan Lynch</name>
<email>nathan_lynch@mentor.com</email>
</author>
<published>2015-04-17T20:51:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=5d38000b3c97a1079734c0b4c5f87d5b935318cd'/>
<id>urn:sha1:5d38000b3c97a1079734c0b4c5f87d5b935318cd</id>
<content type='text'>
When targeting ARMv3 (e.g. rpc) and enabling CONFIG_VDSO we get:

arch/arm/vdso/datapage.S:13: Error: selected processor does not
support ARM mode `bx lr'

One fix considered was to use 'ldr pc,lr' for such configurations, but
since the VDSO is unlikely to be useful for pre-v7 hardware, just make
it depend on CONFIG_CPU_V7.

Reported-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Nathan Lynch &lt;nathan_lynch@mentor.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>Merge branches 'misc', 'vdso' and 'fixes' into for-next</title>
<updated>2015-04-14T21:28:25+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2015-04-14T21:28:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=c848791f0336914a3081ea3fe029cf177d81de81'/>
<id>urn:sha1:c848791f0336914a3081ea3fe029cf177d81de81</id>
<content type='text'>
Conflicts:
	arch/arm/mm/proc-macros.S
</content>
</entry>
<entry>
<title>ARM: 8276/1: Make CPU_DCACHE_DISABLE depend on !SMP</title>
<updated>2015-04-02T09:06:35+00:00</updated>
<author>
<name>Florian Fainelli</name>
<email>f.fainelli@gmail.com</email>
</author>
<published>2015-01-09T18:34:43+00:00</published>
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<id>urn:sha1:e1e2f6e4c5759aab3a8cfb1a0c19017ea770dfd2</id>
<content type='text'>
Enabling CPU_DCACHE_DISABLE on a SMP capable system will prevent the
kernel from booting because of the following ldrex instruction in
arch_spin_lock:

(gdb) x/10i $pc
=&gt; 0xc053cfa8 &lt;_raw_spin_lock+4&gt;:       ldrex   r3, [r0]
   0xc053cfac &lt;_raw_spin_lock+8&gt;:       add     r2, r3, #65536  ; 0x10000

which is taken by the very first printk call:

    at /home/fainelli/work/linux/arch/arm/include/asm/spinlock.h:65
    fmt=0xc0637650 " 01 66Booting Linux on physical CPU 0x%xn", args=&lt;incomplete type&gt;)
    at kernel/printk/printk.c:1525
    fmt=0xc05370f4 &lt;printk+52&gt; " 24320215342 04340235344 20320215342 36377/341 17") at kernel/printk/printk.c:1688

ldrex requires exclusive monitor(s) (local or global) which are no longer
working when the Data cache is disabled in CP15 and will just hang the CPU
there.

Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: 8332/1: add CONFIG_VDSO Kconfig and Makefile bits</title>
<updated>2015-03-27T22:20:45+00:00</updated>
<author>
<name>Nathan Lynch</name>
<email>nathan_lynch@mentor.com</email>
</author>
<published>2015-03-25T18:16:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/BMC/Intel-BMC/linux.git/commit/?id=e5b61deb3af465f11db7e5e11944ba00a33ece1f'/>
<id>urn:sha1:e5b61deb3af465f11db7e5e11944ba00a33ece1f</id>
<content type='text'>
Allow users to enable the vdso in Kconfig; include the vdso in the
build if CONFIG_VDSO is enabled.  Add 'vdso_install' target.

Signed-off-by: Nathan Lynch &lt;nathan_lynch@mentor.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
</feed>
