Intel OpenBMC Linux kernel source tree (mirror) https://git.radix-linux.su/BMC/Intel-BMC/linux.git/atom?h=dev 2015-02-01T16:51:12+00:00 2015-02-01T16:51:12+00:00 Olof Johansson olof@lixom.net 2015-02-01T16:51:12+00:00 urn:sha1:28111dda37e653781efc73c06229f006739b3982 Merge "Third Round of Renesas ARM Based SoC Fixes for v3.19" from Simon Horman: * Instantiate GIC from C board code in legacy builds on r8a7790 and r8a73a4 * tag 'renesas-soc-fixes3-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7790: Instantiate GIC from C board code in legacy builds ARM: shmobile: r8a73a4: Instantiate GIC from C board code in legacy builds Signed-off-by: Olof Johansson <olof@lixom.net> 2015-01-29T08:52:38+00:00 Magnus Damm damm+renesas@opensource.se 2015-01-29T07:25:32+00:00 urn:sha1:77cf5166f21c3b73b04571311dc89a327424f594 As of commit 9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq domain."), the Lager legacy board support is known to be broken. The IRQ numbers of the GIC are now virtual, and no longer match the hardcoded hardware IRQ numbers in the legacy platform board code. To fix this issue specific to non-multiplatform r8a7790 and Lager: 1) Instantiate the GIC from platform board code and also 2) Skip over the DT arch timer as well as 3) Force delay setup based on DT CPU frequency With these 3 fixes in place interrupts on Lager are now unbroken. Partially based on legacy GIC fix by Geert Uytterhoeven, thanks to him for the initial work. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> 2015-01-29T00:34:51+00:00 Magnus Damm damm+renesas@opensource.se 2015-01-28T12:46:45+00:00 urn:sha1:974b072f71e350bf2c5fb9cfd5c6c9d341a53300 As of commit 9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq domain."), the APE6EVM legacy board support is known to be broken. The IRQ numbers of the GIC are now virtual, and no longer match the hardcoded hardware IRQ numbers in the legacy platform board code. To fix this issue specific to non-muliplatform r8a73a4 and APE6EVM: 1) Instantiate the GIC from platform board code and also 2) Skip over the DT arch timer as well as 3) Force delay setup based on DT CPU frequency With these 3 fixes in place interrupts on APE6EVM are now unbroken. Partially based on legacy GIC fix by Geert Uytterhoeven, thanks to him for the initial work. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> 2014-12-09T22:38:28+00:00 Linus Torvalds torvalds@linux-foundation.org 2014-12-09T22:38:28+00:00 urn:sha1:6cd94d5e57ab97ddd672b707ab4bb639672c1727 Pull ARM SoC platform changes from Arnd Bergmann: "New and updated SoC support, notable changes include: - bcm: brcmstb SMP support initial iproc/cygnus support - exynos: Exynos4415 SoC support PMU and suspend support for Exynos5420 PMU support for Exynos3250 pm related maintenance - imx: new LS1021A SoC support vybrid 610 global timer support - integrator: convert to using multiplatform configuration - mediatek: earlyprintk support for mt8127/mt8135 - meson: meson8 soc and l2 cache controller support - mvebu: Armada 38x CPU hotplug support drop support for prerelease Armada 375 Z1 stepping extended suspend support, now works on Armada 370/XP - omap: hwmod related maintenance prcm cleanup - pxa: initial pxa27x DT handling - rockchip: SMP support for rk3288 add cpu frequency scaling support - shmobile: r8a7740 power domain support various small restart, timer, pci apmu changes - sunxi: Allwinner A80 (sun9i) earlyprintk support - ux500: power domain support Overall, a significant chunk of changes, coming mostly from the usual suspects: omap, shmobile, samsung and mvebu, all of which already contain a lot of platform specific code in arch/arm" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits) ARM: mvebu: use the cpufreq-dt platform_data for independent clocks soc: integrator: Add terminating entry for integrator_cm_match ARM: mvebu: add SDRAM controller description for Armada XP ARM: mvebu: adjust mbus controller description on Armada 370/XP ARM: mvebu: add suspend/resume DT information for Armada XP GP ARM: mvebu: synchronize secondary CPU clocks on resume ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume ARM: mvebu: Armada XP GP specific suspend/resume code ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume ARM: mvebu: implement suspend/resume support for Armada XP clk: mvebu: add suspend/resume for gatable clocks bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration bus: mvebu-mbus: suspend/resume support clocksource: time-armada-370-xp: add suspend/resume support irqchip: armada-370-xp: Add suspend/resume support ARM: add lolevel debug support for asm9260 ARM: add mach-asm9260 ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf power: reset: imx-snvs-poweroff: add power off driver for i.mx6 ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A ... 2014-10-27T00:48:07+00:00 Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com 2014-10-26T14:20:27+00:00 urn:sha1:335204dfb83b3105cf4a666d1ad024917831cbdc The information is already included in the COPYING file in the kernel sources root directory, we don't want to modify all source files when the FSF will move to a new address, and I'm tired of seeing the related checkpatch.pl warnings. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> 2014-10-24T01:53:30+00:00 Magnus Damm damm+renesas@opensource.se 2014-10-05T23:59:20+00:00 urn:sha1:27f3c70874fc1d114e26c807e900fec4b50b1217 Update the delay code to include arch timer checks for CA7. From a arch timer availability perspective CA7 should be treated same as CA15. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> 2014-09-09T15:09:35+00:00 Arnd Bergmann arnd@arndb.de 2014-09-09T15:09:35+00:00 urn:sha1:138310e18b70caed1b7acf02a2c97170dcb3c55d Pull "Third Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman: * Initial r8a7794 SoC support * Support Cortex-A7 in shmobile_init_delay() Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'renesas-soc3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Initial r8a7794 SoC support ARM: shmobile: support Cortex-A7 in shmobile_init_delay() 2014-09-05T08:23:45+00:00 Ulrich Hecht ulrich.hecht+renesas@gmail.com 2014-09-04T14:02:27+00:00 urn:sha1:0dc50fd3dc4a70d0d317103188c129d378125643 Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> 2014-08-22T02:31:56+00:00 Magnus Damm damm+renesas@opensource.se 2014-08-20T13:03:12+00:00 urn:sha1:7dd4cfd7f8c2976a8d65022146386480474501ca All ARM mach-shmobile SoCs and boards now rely on DTS for CPU Frequency information, so remove the unused function shmobile_setup_delay(). While at it, make the function shmobile_setup_delay_hz() static. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> 2014-06-16T10:52:00+00:00 Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com 2014-05-21T13:31:05+00:00 urn:sha1:edc8fb1d6ebdfc4efa009073586d3567c3368475 The of_find_compatible_node() function returns a new reference to the found node. Instead of just adding of_node_put() calls, simplify the code by moving the CPU identification logic inside the loop over cpu nodes, in order to lower complexity from O(n) to O(1) by replacing of_find_compatible_node() calls with of_device_is_compatible(). Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>