BMC/Intel-BMC/linux.git/arch/arm/mach-imx/system.c, branch dev

ARM: imx: clean up machine mxc_arch_reset_init_dt reset init

2014-11-21T23:39:36+00:00

System restart mechanism has been changed with the introduction of "kernel restart handler call chain support". The imx2 watchdog based restart handler has been moved to the driver, and these restart can be removed from the machine layer. This patch cleans up the device tree version machine reset init with mxc_arch_reset_init_dt and removes corresponding .restart handler, for the .init_machine that can be handled by system default after removing the mxc_arch_reset_init_dt, the .init_machine is also removed. Signed-off-by: Jingchang Lu Signed-off-by: Shawn Guo

ARM: i.MX system: Add a reset fallback if base address of watchdog is not set

2014-07-18T08:10:13+00:00

This patch adds a reset fallback if base address of watchdog is not set. This is intended for a targets not compatible with imx-21 watchdog, i.MX1 for example. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo

ARM: i.MX system: Simplify handling watchdog clock

2014-07-18T08:10:13+00:00

This patch simplifies handling watchdog clock a bit. As an additional change, now we properly check WDT clock in a reset function. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo

ARM: l2c: imx: remove direct write to power control register

2014-05-29T23:49:22+00:00

Now that we handle this in core code, we don't need platforms enabling the low power modes directly. Acked-by: Shawn Guo Signed-off-by: Russell King

ARM: l2c: fix register naming

2014-05-29T23:48:43+00:00

We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Acked-by: Tony Lindgren Acked-by: Linus Walleij Acked-by: Shawn Guo Acked-by: Stephen Warren Signed-off-by: Russell King

ARM: l2c: remove unnecessary UL-suffix to mask values

2014-05-22T15:38:43+00:00

They're u32, they're not unsigned long. The UL suffix is not required here. Acked-by: Shawn Guo Signed-off-by: Russell King

ARM: imx: improve mxc_restart() on the SRC bit writes

2013-11-11T14:58:43+00:00

The current comment in the code does not make it clear why the double writes on SRC bit is needed. Let's quote the errata to get it clear. Also, to ensure there are at least 2 writes happen in the same one 32kHz period, we actually need 3 writes. Let's add the third one. Signed-off-by: Shawn Guo

ARM: imx: remove imx_src_prepare_restart() call

2013-11-11T14:58:43+00:00

There is ~10% possibility that the following emergency restart command fails to reboot imx6q. $ echo b > /proc/sysrq-trigger The IMX restart routine mxc_restart() assumes that it will always run on primary core, and will call imx_src_prepare_restart() to disable secondary cores in order to get them come to online in the following boot. However, the assumption is only true for normal kernel_restart() case where migrate_to_reboot_cpu() will be called to migrate to primary core, but not necessarily true for emergency_restart() case. So when emergency_restart() calls into mxc_restart() on any secondary core, system will hang immediately once imx_src_prepare_restart() is called to disabled secondary cores. Since emergency_restart() is defined as a function that is safe to call in interrupt context, we cannot just call migrate_to_reboot_cpu() to fix the issue. Fortunately, we just found that the issue can be fixed at imx6q platform level. We used to call imx_src_prepare_restart() to disable all secondary cores before resetting hardware. Otherwise, the secondary will fail come to online in the reboot. However, we recently found that after commit 6050d18 (ARM: imx: reset core along with enable/disable operation) comes to play, we do not need to reset the secondary cores any more. That said, mxc_restart() now can run on any core to reboot the system, as long as we remove the imx_src_prepare_restart() call from mxc_restart(). So let's simply remove imx_src_prepare_restart() call to fix the above emergency restart failure. Reported-by: Jiada Wang Signed-off-by: Shawn Guo

ARM: imx: replace imx6q_restart() with mxc_restart()

2013-10-21T01:36:53+00:00

The imx6q_restart() works fine with normal reboot but will run into problem with emergency reboot like sysrq-b. In that case, of_iomap() gets called from interrupt context and hence triggers the BUG_ON in __get_vm_area_node(). Actually, since commit c1e31d1 (ARM: imx: create mxc_arch_reset_init_dt() for DT boot), imx6q/dl should try to use mxc_restart() by calling mxc_arch_reset_init_dt() beforehand, where things like of_iomap() can be done. The patch updates mxc_restart() a little bit to get it work for imx6q/dl and kill imx6q_restart() completely. Reported-by: Nathan Lynch Signed-off-by: Shawn Guo

ARM: imx: i.mx6d/q: disable the double linefill feature of PL310

2013-09-17T02:04:24+00:00

The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 But according to ARM PL310 errata: 752271 ID: 752271: Double linefill feature can cause data corruption Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 Workaround: The only workaround to this erratum is to disable the double linefill feature. This is the default behavior. without this patch, you will meet the following error when run the memtester application at: http://pyropus.ca/software/memtester/ FAILURE: 0x00100000 != 0x00200000 at offset 0x01365664. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365668. FAILURE: 0x00100000 != 0x00200000 at offset 0x0136566c. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365670. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365674. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365678. Signed-off-by: Jason Liu Signed-off-by: Shawn Guo